參數(shù)資料
型號: T7230A
廠商: Lineage Power
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 51/110頁
文件大?。?/td> 752K
代理商: T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
47
Lucent Technologies Inc.
CEPT Time Slot 0 FAS/NOT FAS Control Bits
(continued)
NOT FAS Sa-Bit Sources
(continued)
The receive Sa data is always present at:
1.
The system transmit interface.
When in CEPT format, and PR3, bit 1 = 1, the receive framer will copy its NOT FAS time slot 0 into time slot 0 of
both the NOT FAS and the FAS frames that appear on the system interface (DRA, DRB).
5-4938(F)
1. Normal transmission of FAS and NOT FAS time slot 0 data from the system transmit port of the T7230A.
2. Double NOT FAS transmission time slot 0 data from the system transmit port if the T7230A: PR3, bit 1 = 1.
3. Double NOT FAS reception time slot 0 data from the system receive port of the T7230A: PR3, bit 1 = 1 and PR6, bit 6 = 1.
4. The transmit framer arbitrarily assigns these frames as NOT FAS frames and transmits the Sa bit to the line.
5. Or, the transmit framer arbitrarily assigns these frames as NOT FAS frames and transmits the Sa bit to the line.
Note: If PR6, bit 6 = 1 and PR3, bit 1 = 0, then the transmit framer will always look for the alternating 10 pattern in bit 2 of time slot 0 to deter-
mine the FAS and NOT FAS frames.
Figure 12. CEPT AFS and NOT FAS System Interface Format
2.
The Sa status register.
The selected Sa bit for facility data link interface is always present at the receive facility data link interface. In the
LFA state, RFD = 1.
DX
2
DR
3
FS
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
4
5
DX
1
FAS
FAS
FAS
FAS
FAS
NOT
NOT
FAS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
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