參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 87/110頁
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
83
Lucent Technologies Inc.
Register Structure
(continued)
Parameter/Control Registers
(continued)
On-Demand Transmit Register 2 (PR4)
Table 59. On-Demand Register 2 Bits Decoding
Transmit Signal
Bit 7
Bit 6
Bit 5
DLB1
X
Bit 4
DLB0
X
Bit 3
Bit 2
Bit 1 Bit 0
Transmit System Channel Squelch:
DDS mode transmits the MOS code (00011010).
All other modes transmit the AIS (all ones) pattern.
Transmit System Signaling Squelch:
CEPT only: AIS is written into time slot 16 of the transmit system
data.
Receive Framer Reframe:
Force the LFA state in the receive framer and initiate a search of
frame alignment.
Subsequent reframe commands must have this bit in the 0 state first.
Receive Signaling Inhibit:
Inhibit updating of the receive signaling buffer.
Line Loopback
Payload Loopback with Pass-Through F Bits:
Received channelized-payload data, CRC checksum bits and F bits
are looped backed to the line. The system’s facility data link bit
stream is inserted into the looped data and then transmitted to the
line.
Inserting a new facility data link into its F-bit position in ESF mode
does not change the CRC-6 checksum (all F-bit positions are set to
1 when calculating the CRC-6 checksum).
This mode is NOT recommended for CEPT framing format.
The receive framer processes and monitors the incoming line data
autonomously to this loopback mode and transmits the formatted
data to the system in the normal format via the CHI.
Payload Loopback with Regenerated F Bits:
As defined in the Lucent Technologies TR 54016, Requirements for
Interfacing Digital Terminal Equipment to Services Employing the
Extended Superframe Format, September 1989 edition, the
received channelized-payload data is looped back to the line. The
framing bits are generated within the transmit framer sections at the
point of the PLB. The regenerated framing information includes the
F-bit pattern, the CRC checksum bit, and the system’s facility data
link bit stream.
This loopback mode can be used with the CEPT framing mode. The
entire time slot 0 data (FAS and NOT FAS) is regenerated by the
transmit framer.
The receive framer processes and monitors the incoming line data
autonomously to this loopback mode and transmits the formatted
data to the system in the normal format via the CHI.
Transmit Line Loopback On Code: 001 (with Valid F-bit Informa-
tion).
Transmit Line Loopback Off Code: 00001 (with valid F-bit Infor-
mation).
X
X
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
X
X
X
0
1
1
0
X
X
X
X
X
X
X
X
X
X
1
1
X
X
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
X
X
X
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相關代理商/技術參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動開關 ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關 ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
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