參數(shù)資料
型號(hào): T7230A
廠(chǎng)商: Lineage Power
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 57/110頁(yè)
文件大?。?/td> 752K
代理商: T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
53
Lucent Technologies Inc.
Alarms and Performance Monitoring
(continued)
7.
The
continuous E-bit
alarm (CON-E) is asserted when the receive framer detects:
A.
Five consecutive seconds where each 1 second interval contains
991 received E bits = 0 events.
B.
Simultaneously no LFA occurred.
C.
No A bit = 1 was received.
D.
Neither Sa6_F
hex
nor Sa6_E
hex
codes were detected.
The five second timer is started when:
E.
F.
G.
CRC-4 multiframe alignment is achieved.
A = 0 is detected.
Neither Sa6
_
F
hex
nor Sa6
_
E
hex
is detected.
The five second counter is restarted when:
H.
LFA occurs, or
I.
990 E bit = 0 events occurred in 1 second, or
J.
An A bit = 1, is detected, or
K.
A valid Sa6_F
hex
or Sa6_E
hex
code was detected.
This alarm is disabled when:
L.
M.
N.
O.
LFA occurs.
or
990 E bit = 0 events occurred in 1 second, or
An A bit = 1 is detected, or
The Sa6_F
hex
or Sa6_E
hex
code was detected.
8.
Failed state
alarm or the
unavailable state alarm
.
A.
The default mode asserts this alarm bit upon detection of ten consecutive severely errored second
events and deasserts this alarm bit upon detection of ten consecutive seconds that were not severely
errored. The corresponding performance counters are incremented appropriately.
B.
Optionally, the T7230A can be programmed to process the unavailable state at the onset of the
unavailable state (at the beginning of the ten consecutive severely error interval), and inhibit the
increment of the severely errored and errored seconds counters for the duration of the unavailable state.
In this mode, the contents of the performance counters contains information delayed by ten seconds.
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參數(shù)描述
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