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參數(shù)資料
| 型號： | T7230A |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 20/110頁 |
| 文件大?。?/td> | 752K |
| 代理商： | T7230A |
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Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
16
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions for the 68-Pin Package
(continued)
1. I
u
indicates an internal pull-up.
Pin
57
Symbol
DRA_BUF
Type
1
I
Name and Function
Receive CHI Data Port A.
Serial input system data at 2.048 Mbits/s or
4.096 Mbits/s.
Buffer Underflow.
In framer mode (FRMMOD = 0), this may be used in
performance monitoring to indicate an underflow event from an external
elastic store.
Transmit CHI Data Port A.
Serial output system data at 2.048 Mbits/s or
4.096 Mbits/s. This port is forced into a high-impedance state for all inac-
tive time slots.
Receive Data.
In framer mode (FRMMOD = 0), this is the serial unirail out-
put data from the receive framer at 1.544 Mbits/s (DS1) or 2.048 Mbits/s
(CEPT) rates.
Output CHI Frame Sync.
In the CHI master mode, the T7230A’s receive
CHI circuit generates an 8 kHz frame sync on this pin for use on the CHI.
Ground.
CHI Frame Sync.
8 kHz frame sync from a CHI master.
CHI Transmit/Receive Clock.
2.048/4.096/8.192 MHz CHI clock signal.
The PLLCK signal should be phase-locked to CLKXR.
Divided-Down Receive Line Clock.
8 kHz clock signal derived from the
RLCK input signal.
Receive Framing Bit.
In DS1 framing formats, this pin outputs the value
of the framing bit associated with the current CHI frame. The value is valid
for the duration of the CHI frame. In CEPT mode, this pin is forced to a
1 state.
Transmit Facility Data Link Clock.
In DS1-DDS with data link access,
this is an 8 kHz clock signal. Otherwise, this is a 4 kHz clock signal.
Transmit Facility Data Link.
Serial input facility data link bit stream for
insertion into the transmit line data stream by the transmit framer. In DS1-
DDS with data link access, this is an 8 kbits/s signal. Otherwise, this is a
4 kbits/s signal.
Receive Facility Data Link Clock.
In DS1-DDS with data link access, this
is an 8 kHz clock signal. Otherwise, this is a 4 kHz clock signal.
Receive Facility Data Link.
Serial output facility data link bit stream
extracted from the receive line data stream by the receive framer. In DS1-
DDS with data link access, this is an 8 kbits/s signal. Otherwise, this is a
4 kbits/s signal. During a loss of frame alignment, the receive framer will
force this pin to a 1 state.
58
DXA_RD
O
59
OFS
O
60
61
62
V
SS
FS
CLKXR
—
I
I
63
DRLCK
O
64
FRBIT
O
65
XFCK
O
66
XFD
I
67
RFCK
O
68
RFD
O
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