參數(shù)資料
型號(hào)： T7230A
廠(chǎng)商： Lineage Power
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 56/110頁(yè)
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
52
Lucent Technologies Inc.
Alarms and Performance Monitoring
(continued)
3.
Alarm Indication Signal
(AIS). The T7230A’s receive framer detects an incoming alarm indication signal as
defined in Table 26.
4.
The slip condition is defined as the state in which the receive framer write address pointer and the transmit
concentration highway interface read address pointer (to the elastic store buffer) are within an invalid range
1
.
A.
The negative slip (slip-O) alarm indicates the receive line clock (RLCK) — system clock (CLKXR)
monitoring circuit detects a state of overflow caused by the frequency of RLCK being greater than the
frequency of CLKXR. One system frame is deleted.
B.
The positive slip (slip-U) alarm indicates the line clock (RLCK) — system clock (CLKXR) monitoring
circuit detects a state of underflow caused by the frequency of CLKXR being greater than frequency of
RLCK. One system frame is repeated.
5.
The
loss of receive clock
(LORLCK) alarm is asserted when an interval of 250
μ
s has expired with no
transition of RLCK detected. The alarm is disabled on the first transition of RLCK. The T7230A's receive framer
cannot extract the receive clock from the pulses it receives from the receive line interface but depend on the
receive line interface to provide a valid receive line clock signal on RLCK. In the loss of receive clock state, the
status registers will be clocked by a 2 MHz internal clock signal derived from the CLKXR input signal.
The
loss of transmit clock
(LOXLCK) alarm is asserted when an interval of 250
μ
s
has expired with no
transition of PLLCK is detected
2
. The alarm is disabled on the first transition of PLLCK.
6.
1. The invalid pointer range is 1 to 3 byte for DS1 and 6 bytes for CEPT.
2. There is no transmission of line data while LOXLCK = 1.
Table 26. Alarm Indication Signal Conditions
Framing Format
Activation Criteria
T1
The incoming signal has two or fewer zeros in each of two consecutive
double-frame periods (386 bits). AIS is cleared if each of two consecutive
double-frame periods contains three or more zeros.
As described in Draft prETS 300 233:1992 section 8.2.2.4, loss of frame
alignment occurs and the reception of 512 bit periods containing two or less
binary 0s.
As described in ITU Rec. G.775, the incoming signal has two or fewer zeros
in each of two consecutive double-frame periods (512 bits). AIS is cleared if
each of two consecutive double-frame periods contains three.
CEPT ETSI
CEPT ITU
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動(dòng)開(kāi)關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開(kāi)關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類(lèi)型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動(dòng)開(kāi)關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開(kāi)關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類(lèi)型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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