
Revision 1.2
7
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Table of Contents
1.0
Signal/Pin Connection and Description
1.1
CONNECTION DIAGRAMS ......................................................................................................16
1.2
BUFFER TYPES AND SIGNAL/PIN DIRECTORY ....................................................................20
1.3
PIN MULTIPLEXING .................................................................................................................20
1.4
DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................22
1.4.1
LPC Interface ..............................................................................................................23
1.4.2
ACCESS.bus (ACB) Interface (PC87413 and PC87417) ...........................................23
1.4.3
X-Bus Extension (PC87416 and PC87417) ................................................................23
1.4.4
Serial Port 1 and Serial Port 2 (UART1 and UART2) .................................................24
1.4.5
Parallel Port ................................................................................................................25
1.4.6
Floppy Disk Controller (FDC) .....................................................................................26
1.4.7
Keyboard and Mouse Controller (KBC) ......................................................................27
1.4.8
General-Purpose I/O (GPIO) ......................................................................................27
1.4.9
System Wake-Up Control (SWC) ...............................................................................28
1.4.10
Clocks ..........................................................................................................................29
1.4.11
Configuration Straps ...................................................................................................29
1.4.12
Power and Ground ......................................................................................................30
1.5
INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................30
2.0
Power, Reset and Clocks
2.1
POWER .....................................................................................................................................32
2.1.1
Power Planes ..............................................................................................................32
2.1.2
Power States ...............................................................................................................32
2.1.3
Power Connection and Layout Guidelines ..................................................................33
2.2
RESET SOURCES AND TYPES ...............................................................................................34
2.2.1
V
PP
Power-Up Reset ...................................................................................................34
2.2.2
VSB Power-Up Reset ..................................................................................................34
2.2.3
Controller Software Reset (PC87413 and PC87417) ..................................................35
2.2.4
VDD Power-Up Reset ..................................................................................................35
2.2.5
Hardware Reset ...........................................................................................................35
2.2.6
Host Software Reset ....................................................................................................35
2.3
CLOCK GENERATION ..............................................................................................................36
2.3.1
Clock Domains ............................................................................................................36
2.3.2
Clock Generator ..........................................................................................................36
2.3.3
Low Frequency Clock ..................................................................................................37
3.0
Device Architecture and Configuration
3.1
OVERVIEW ...............................................................................................................................38
3.2
CONFIGURATION STRUCTURE AND ACCESS .....................................................................38
3.2.1
The Index-Data Register Pair ......................................................................................38
3.2.2
Banked Logical Device Registers Structure ................................................................39
3.2.3
Standard Configuration Register Definitions ...............................................................40
3.2.4
Standard Configuration Registers ...............................................................................42