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7.0 General-Purpose Input/Output (GPIO) Ports
(Continued)
Revision 1.2
137
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P
Access Control - Limits access to the specific pin from only one of the buses (ACCESS.bus or LPC bus). When access
from a bus is disabled, attempted writes to the Basic Functionality configuration registers (GPCFG1 bits 3-0 and
GPCFG2 bits 6-4, none of which are shown in Figure 36) and to the corresponding bit in the GPDO register are ignored.
Reads from the bits above and from the corresponding bit in the GPDI register are allowed and return the actual bit value.
Bus access is controlled by Bus Control bits (bits 6 and 5). After reset, both bits are ‘0’ and access is allowed from both
ACCESS.bus and LPC bus.
In the PC87414 and PC87416, this feature is irrelevant because only the LPC bus is
available
.
7.2.2
If the output is enabled, the value that is written to the GPDO register is driven to the pin. Reading from the GPDO register
returns its contents regardless of the actual pin value or the port configuration.
The GPDI register is a read-only register. Reading from the GPDI register returns the actual pin value regardless of its
source (the port itself or an external device). Writing to this register is ignored.
Activation of the GPIO module is controlled by device-specific configuration bits. When this module is inactive, access
through the LPC bus to the runtime registers (GPDI and GPDO) is disabled; however, there is no change in the GPDO value
and therefore there is no effect on the outputs of the pins.
Operation
7.3
The enhanced GPIO port (GPIOE) supports system notification based on event detection. This functionality is based on
configuration bits and a bit slice of runtime registers GPEVEN and GPEVST. The configuration and operation of the event
detection capability is shown in Figure 37. System notification is described in Section 7.3.2.
EVENT HANDLING AND SYSTEM NOTIFICATION
Figure 37. Event Detection
7.3.1
Each pin in the GPIO port is a potential input event source. The event detection can trigger a system notification upon pre-
determined behavior of the source pin. The GPCFG1 register determines the event detection trigger type for the system
notification.
Event Configuration
Event
Enable
Event Polarity
Input
Debouncer
1
0
Event
Pending
Internal
Bus
0
1
Pin
Level =1
Write 1 to Clear
Status
Rising Edge or
High Level =1
Rising
Edge
Detector
GPIO Pin Configuration Register 1
(GPCFG1)
Event Type
Event
Debounce
Enable
R/W
Bit 6
Bit 5
Bit 4
Indication
Reset
Set
GPIO Event Indication to SWC
Read
GPIO
GPIO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
| PC87415 | PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | PCI-IDE DMA Master Mode Interface Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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