
3.0 Device Architecture and Configuration
(Continued)
Revision 1.2
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P
3.7.1
This register contains the identity number of the device family. The PC8741x family is identified by the value EEh.
Power Well:V
SB
Location:Index 20h
Type:
RO
ServerI/O ID Register (SID)
3.7.2
Power Well:V
SB
Location:Index 21h
Type:
Varies per bit
ServerI/O Configuration 1 Register (SIOCF1)
Bit
7
6
5
4
3
2
1
0
Name
Family ID
Reset
EEh
Bit
Description
7-0
Family ID.
These bits identify a family of devices with similar functionality but with different implemented
options.
Bit
Name
Reset
7
6
5
4
3
2
1
0
LOCKMCF
0
LOCKGCF
0
Reserved
IOWAIT
HSWRST
0
GLOBEN
1
0
1
0
0
Bit
Type
Description
7
R/W1S
LOCKMCF (Lock Multiplexing Configuration).
When set to 1, this bit locks the configuration of
registers SIOCF1, SIOCF2, SIOCF3, SIOCF4 and SIOCF5 by disabling writing to all bits in these
registers (including the LOCKMCF bit itself), except for the LOCKGCF, HSWRST and GLOBEN bits of
SIOCF1. Once set, this bit can be cleared either by V
DD
Power-Up reset (or Hardware reset) or by V
SB
Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on
page 128). In addition, this bit is cleared by setting the UNLOCKM bit in the ACBLKCTL register
(
PC87413 and PC787417
).
0: R/W bits are enabled for write (default)
1: All bits are RO
6
R/W1S
LOCKGCF (Lock GPIO Pins Configuration).
When set to 1, this bit locks the configuration registers
of all the GPIO pins (see Section 3.14.2 on page 71) by disabling writing to all their bits (including the
LOCKGCF bit itself). Once set, this bit can be cleared either by V
DD
Power-Up reset (or Hardware
reset) or by V
SB
Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see
Section 6.3.4 on page 128). In addition, this bit is cleared by setting the UNLOCKG bit in the
ACBLKCTL register
(
PC87413 and PC787417
)
.
0: R/W bits are enabled for write (default)
1: All bits are RO
5-4
Reserved
(must be ‘01’).
3-2
R/W or
RO
IOWAIT (Number of I/O Wait States).
These bits set the number of wait states for I/O transactions
through the LPC bus.
Bits
3 2
Number of wait states
0 0:
0 (Zero - default)
0 1:
2
1 0:
6
1 1:
12