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參數(shù)資料
| 型號(hào)： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務(wù)器和工作站 |
| 文件頁(yè)數(shù)： | 124/257頁(yè) |
| 文件大?。?/td> | 3163K |
| 代理商： | PC87413 |
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6.0 ACCESS.bus Interface
(Continued)
www.national.com
124
Revision1.2
P
Reset Slave Transaction
This is a broadcast transaction to the General Call address (00h) that resets the ACCESS.bus Interface logic and the data
registers (the configuration registers are not affected) and reloads the current slave address by starting a slave address set-
up process (see Section 6.2.6 on page 119). PEC is not supported for this transaction. Since this is a broadcast transaction,
all slave devices connected to the ACCESS.bus respond to it.
Write Internal Transaction
This transaction writes a byte of data to a register of a functional block of the PC8741x device. The functional block is se-
lected by the Logical Device Number for the ACCESS.bus (see Table 33 on page 123). The specific register is accessed
using the 8-bit offset address (from the base of the functional block). If PEC is supported, the master sends a PEC byte at
the end of the transaction.
If the selected Logical Device is not powered (the V
DD
supply is off), the PC8741x device generates a NACK bit at the end
of the Command byte, sets the OFFLDN bit in the ACBCST register (see Section 6.3.2 on page 127) and aborts the trans-
action.
Read Internal Transaction
This transaction reads a byte of data from a register of a functional block of the PC8741x device. The functional block is
selected by the Logical Device Number for the ACCESS.bus (see Table 33 on page 123). The specific register is accessed
using the 8-bit offset address (from the base of the functional block). This transaction is executed in two phases:
G
The master executes an ACCESS.bus write transaction, which conveys the Command (Read) and Offset Address
information to the PC8741x device. During this phase, the data is read from the specific register into the Read Buffer.
This phase has no Stop Condition.
G
Following a Restart condition, the master executes an ACCESS.bus read transaction. During this phase the data is
transferred from the Read Buffer to the master. At the end of this phase, the PC8741x device returns a PEC byte if
required by the master. The calculated PEC value is based on the bytes transferred during both phases.
If the selected Logical Device is not powered (the V
DD
supply is off), the PC8741x device generates a NACK bit at the end
of the Command byte, sets the OFFLDN bit in the ACBCST register (see Section 6.3.2 on page 127) and aborts the trans-
action.
S
P
General Call Address
(00h)
Reset & Reload Slave Address
A
(06h)
= Start condition
= ACK by slave
S
A
A
= Stop condition
P
P
Slave Address
(S.A, Write)
Command
(Int, Write, LDN)
Offset Address
(OA7-OA0)
Data
PEC
S
A
A
A
A
A
= Start condition
= ACK by slave
S
A
= Stop condition
P
P
Slave Address
(S.A, Write)
Command
(Int, Read, LDN)
Offset Address
(OA7-OA0)
Data
PEC
S
A
A
A
A
N
= Start condition
= Restart condition
S
= Stop condition
P
Slave Address
(S.A, Read)
R
A
= ACK by slave
A
R
A
= ACK by master
N
= NACK by master
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PDF描述 |
|---|---|
| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
| PC87415 | PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | PCI-IDE DMA Master Mode Interface Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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