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參數(shù)資料
| 型號： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務(wù)器和工作站 |
| 文件頁數(shù)： | 125/257頁 |
| 文件大小： | 3163K |
| 代理商： | PC87413 |
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6.0 ACCESS.bus Interface
(Continued)
Revision 1.2
125
www.national.com
P
Write External Transaction (PC87417)
This transaction writes a byte of data to a memory device or to an I/O port connected to the X-Bus. The chip-select for the
device is selected by the XBCSN field in the command byte. The specific memory location or I/O port register is accessed
using a 27-bit offset address (from the base of the chip-select). The 27-bit offset address is broken into four bytes: XA26-
XA24 in the Command byte and XA23-XA16, XA15-XA8 and XA7-XA0 in three successive Offset Address bytes. If PEC is
supported, the master sends a PEC byte at the end of the transaction.
Read External Transaction (PC87417)
This transaction reads a byte of data from a memory device or from an I/O port connected to the X-Bus. The chip-select for
the device is selected by the XBCSN field in the command byte. The specific memory location or I/O port register is accessed
using a 27-bit offset address (from the base of the chip-select). The 27-bit offset address is broken in four bytes: XA26-XA24
in the Command byte and XA23-XA16, XA15-XA8 and XA7-XA0 in three successive Offset Address bytes. This transaction
is executed in two phases:
G
The master executes an ACCESS.bus write transaction, which conveys the Command (Read), chip-select and Offset
Address information to the PC8741x device. During this phase, the data is read from the specific memory location or
I/O port register into the Read Buffer. This phase has no Stop Condition.
G
Following a Restart condition, the master executes an ACCESS.bus read transaction. During this phase the data is
transferred from the Read Buffer to the master. At the end of this phase, the PC8741x device returns a PEC byte if
required by the master. The calculated PEC value is based on the bytes transferred during both phases.
6.2.10
The ACCESS.bus uses the internal bus of the PC8741x device to access the internal modules (except its own registers) or
to bridge transactions to the X-Bus (see “Block Diagram” on page 1). Since the same internal bus is also used independently
by the LPC bus, the duration of the ACCESS.bus use of the internal bus is held to a minimum.
At the highest ACBCLK frequency (100 KHz), the longest ACCESS.bus transaction (Read External) takes at least 750
μ
s
to complete. In order not to stall the internal bus for such a long time, the ACCESS.bus transactions are executed as follows:
Transaction Execution
G
Write - data is written through the internal bus at the end of the transaction after the Stop condition is detected; the
next ACCESS.bus transaction can start immediately while the present data is written through the internal bus.
G
Read - data is read through the internal bus during the second part of the transaction (beginning with Restart), after
the Slave Address is received and before it is acknowledged (ACK); while the data is read through the internal bus,
the ACBCLK signal is held low, indicating to the ACCESS.bus master that PC8741x device is not ready (see Section
6.2.7 on page 120).
The duration of the ACCESS.bus transaction through the internal bus is longer for external access (X-Bus devices -
PC87417
) than for internal access (internal modules of the PC8741x device). If wait states are configured for the module or
X-Bus access, their duration must be added to the internal bus transaction time. When the XRDY signal is in use, its delay
must also be accounted for.
If an LPC transaction started before an ACCESS.bus transaction, the execution of the ACCESS.bus transaction through the
internal bus is withheld until the end of the LPC transaction.
P
Slave Address
(S.A, Write)
Command
Offset Address
(XA23-XA16)
Data
PEC
(Ext, Write, XA26-24)
S
A
A
A
A
A
= Start condition
= ACK by slave
S
A
= Stop condition
P
Offset Address
(XA15-XA8)
A
Offset Address
(XA7-XA0)
A
P
Slave Address
(S.A, Write)
Command
Offset Address
(XA23-XA16)
Data
PEC
S
A
(Ext, Read, XA26-24)
A
A
A
N
= Start condition
= Restart condition
S
= Stop condition
P
Slave Address
(S.A, Read)
R
A
= ACK by slave
A
R
A
= ACK by master
N
= NACK by master
Offset Address
A
Offset Address
A
(XA15-XA8)
(XA7-XA0)
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PDF描述 |
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| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
| PC87415 | PCI-IDE DMA Master Mode Interface Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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