
2.0 Power, Reset and Clocks
(Continued)
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P
2.3
CLOCK GENERATION
2.3.1
The PC8741x devices have five clock domains, as shown in Table 6.
Clock Domains
The LPC and Legacy clock domains, and the modules using them, are powered by the Main power plane. Therefore, these
two clock domains are only active when the V
DD
power supply is on; however, if the Legacy clock domain is sourced by the
Clock Generator, it is active also during the time V
DD
power supply is off.
The Standby and Output clock domains are sourced by the Clock Generator, which is supplied by the Standby power plane.
These two clock domains are active while the V
SB
power supply is on. Both clock domains require a certain amount of time
to stabilize after V
SB
becomes active. Moreover, if the 32 KHz on-chip crystal oscillator was disabled before V
SB
power-up,
the time required for the clocks to stabilize is t
32KOSC
(see Section 11.5.3 on page 241). The selection of 40 MHz (or its
divisions) or 48 MHz (or its divisions) is set by the CKIN48 strap.
The RTC clock domain is sourced either by a clock input or by the on-chip crystal oscillator, which are supplied by the Backup
power plane. This clock domain is active while either the V
BAT
or V
SB
power supply is on. At V
BAT
or V
SB
power-up, the clock
requires t
32KOSC
to stabilize.
2.3.2
The Clock Generator is the source of the Standby and Output clock domains; it is also the source of the Legacy clock domain
if the 48 MHz clock input is not available. The Clock Generator is fed by the 32.768 KHz from the on-chip crystal oscillator
and supplied by the Standby power plane. It starts generating clock output either after the V
SB
power supply is turned on (if
the 32.768 KHz clock is already stable) or after the 32.768 KHz clock stabilizes (if V
BAT
was inactive previous to V
SB
power-
on), whichever occurs last.
Clock
Generator
Operation
Figure 2 shows a simplified diagram of the Clock Generator.
CLKIN
48 MHz or no clock
Figure 2. Clock Generator - Simplified Diagram
Table 6. Clock Domains of the PC8741x
Clock Domain
Frequency
Source
Usage
LPC
Up to 33 MHz
LPC clock input (LCLK)
LPC bus Interface
Legacy
48 MHz
Clock input (CLKIN) or Clock
Generator
Legacy functions (Serial Ports, Parallel
Port, FDC, KBC)
Output Clock
Up to 40 or 48 MHz
Clock Generator
External Devices
Standby
20 or 24 MHz
Clock Generator
V
SB
-powered functions (ACCESS.bus
and X-Bus Interfaces)
RTC
32.768 KHz
Clock input or on-chip oscillator
(32KX1, 32KX2)
1
1. See Section 8.2 on page 142.
RTC, Clock Generator, SWC, GPIO
Frequency
Multiplier
Crystal
Oscillator
On-chip
32.768 KHz
CKIN48
(strap)
1
0
Divider
Programmable
HFCKOUT
LFCKOUT
X-Bus Extension
ACCESS.bus Interface
by 2
Divide
20/24 MHz
Modules
Legacy
48 MHz
40/48 MHz
1
0
32.768 KHz / 1 Hz
32.768 KHz
1 Hz
RTC
LFCKSEL