
6.0 ACCESS.bus Interface
(Continued)
Revision 1.2
129
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P
Bit
Type
Description
7
R/W1S
VSBLOCK (Configuration Lock Until V
SB
Reset).
Controls the reset source of the following lock bits:
LOCKMCF and LOCKGCF in the SIOCF1 register, LOCKFDS in the SIOCF6 register, LOCKCCF in the
CLOCKCF register, LOCKCFP in all GPCFG1 registers (for each GPIO pin), LOCKIOMP in the XIOCNF
register (
PC87417
), LOCKMMP in the XMEMCNF2 register(
PC87417
), all bits of the RLR register,
LOCKXSCF in the XZM0-XZM3 registers (
PC87417
), LOCKXHP in the HAP0 and HAP1 registers
(
PC87417
), LOCK_TMRRST in the PWTMRCTL register and LOCK_SLP_ENC in the SLP_ST_CFG
register. When set to ‘1’, this bit is cleared only by the V
SB
Power-Up reset.
0: Lock bits cleared by V
DD
Power-Up reset, by Hardware reset or by V
SB
Power-Up reset (default)
1: Lock bits cleared only by V
SB
Power-Up reset
6
R/W
UNLOCKM (Unlock Multiplexing Configuration).
When set to ‘1’, this bit resets the LOCKMCF bit in
the SIOCF1 register, ignoring the setting of the VSBLOCK bit. It always returns ‘0’ when read.
0: Normal operation (default)
1: Reset the LOCKMCF bit
5
R/W
UNLOCKG (Unlock GPIO Configuration).
When set to ‘1’, this bit resets the LOCKGCF bit in the
SIOCF1 register and the LOCKCFP bit in all the GPCFG1 registers (for each GPIO pin), ignoring the
setting of the VSBLOCK bit. It always returns ‘0’ when read.
0: Normal operation (default)
1: Reset the LOCKGCF and all the LOCKCFP bits
4
R/W
UNLOCKF (Unlock Fast Disable Configuration).
When set to ‘1’, this bit resets the LOCKFDS bit in
the SIOCF6 register, ignoring the setting of the VSBLOCK bit. It always returns ‘0’ when read.
0: Normal operation (default)
1: Reset the LOCKFDS bit
3
R/W
UNLOCKC (Unlock Clock Configuration).
When set to ‘1’, this bit resets the LOCKCCF bit in the
CLOCKCF register, ignoring the setting of the VSBLOCK bit. It always returns ‘0’ when read.
0: Normal operation (default)
1: Reset the LOCKCCF bit
2
R/W
UNLOCKX (Unlock X-Bus Configuration).
When set to ‘1’, this bit resets the LOCKIOMP bit in the
XIOCNF register, the LOCKMMP bit in the XMEMCNF2 register, the LOCKXSCF bit in the XZM0-XZM3
registers and the LOCKXHP bit in the HAP0 and HAP1 registers, ignoring the setting of the VSBLOCK
bit (
PC87417
). It always returns ‘0’ when read.
0: Normal operation (default)
1: Reset the LOCKIOMP, LOCKMMP, LOCKXSCF and LOCKXHP bits
1
R/W
UNLOCKR (Unlock RAM Lock Configuration).
When set to ‘1’, this bit resets all the bits of the RLR
register (see Section 3.16.3 on page 88), ignoring the setting of the VSBLOCK bit. It always returns ‘0’
when read.
0: Normal operation (default)
1: Reset all the bits of the RLR register
0
R/W
UNLOCKS (Unlock SWC Configuration).
When set to ‘1’, this bit resets the LOCK_TMRRST bit in the
PWTMRCTL register and the LOCK_SLP_ENC bit in the SLP_ST_CFG register, ignoring the setting of
the VSBLOCK bit. It always returns ‘0’ when read.
0: Normal operation (default)
1: Reset the LOCK_TMRRST and LOCK_SLP_ENC bits