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2
Revision1.2
Features
Bus Interfaces
I
LPC Bus Interface
—
Based on Intel’s
LPC Interface Specification Revi-
sion 1.0, September 29, 1997
—
Synchronous cycles using up to 33 MHz bus clock
—
8-bit I/O and Memory read and write cycles
—
Up to four 8-bit DMA channels
—
Serial IRQ
—
Supports bootable memory
—
Reset input
—
CLKRUN support
—
FWH Transaction support
I
ACCESS.bus (ACB) Interface (
PC87413 and PC87417
)
—
Enables a system controller to access the internal
functions and the X-Bus extension
—
Supports slave operation compatible with:
Intel SMBus
ACCESS.bus
—
Proprietary commands for read/write byte from/to:
Internal register
X-Bus I/O device
X-Bus memory device
—
Slave address:
Two values selected by strap
Programmable through the LPC bus
V
BAT
backed-up
—
Concurrent access with the LPC bus
—
V
SB
powered
—
Optional internal pull-up on the ACBDAT and
ACBCLK pins
I
X-Bus Extension (
PC87416 and PC87417
)
—
Supports I/O and Memory read/write operations
—
8-bit data bus, 28-bit address
—
Multiplexed address-data lines:
Four direct address lines
Partial non-multiplexed option
—
Boot configuration selected by straps
—
Four chip-select outputs, each supporting multiple
zones:
Up to 32 MByte BIOS memory zones
Up to 32 MByte user-defined memory zones
Four user-defined I/O zones
Test port and other I/O ports
—
Optional indirect addressing of memory
—
XRD-XEN or XWR-XR/W mode support
—
Supports both slow and fast devices
—
Accessible from both LPC and ACB buses
—
Programmable protection control over access from
the LPC bus
—
V
SB
powered
—
External Interrupt support via XIRQ pin
I
Configuration Control (via LPC bus)
—
Compliant with
PC01 Specification Revision 0.5,
November 2, 1999
—
Plug and Play (PnP) Configuration register structure
—
Base Address strap to setup the address of the
Index-Data register pair
—
Flexible resource allocation for all logical devices:
Relocatable base address
15 IRQ routing options to serial IRQ
Up to four optional 8-bit DMA channels
—
ACCESS.bus control over pin multiplexing, module
disable and output TRI-STATE for all Legacy mod-
ules (
PC87413 and PC87417
)
Legacy Modules
I
Serial Ports 1 and 2
—
Software compatible with the 16550A and the 16450
—
Supports shadow register for write-only bit monitoring
—
UART data rates up to 1.5 Mbaud
I
IEEE 1284-compliant Parallel Port
—
ECP, with Level 2 (14 mA sink and source output
buffers)
—
Software or hardware control
—
Enhanced Parallel Port (EPP) compatible with EPP
1.7 and EPP 1.9
—
Supports EPP as mode 4 of the Extended Control
Register (ECR)
—
Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
—
Supports a demand DMA mode mechanism and a
DMA fairness mechanism for improved bus utilization
—
Protection circuit that prevents damage to the
parallel port when a printer connected to it powers
up or is operated at high voltages, even if the device
is in power-down state
—
Optional outputs TRI-STATE by external pin
I
Floppy Disk Controller (FDC)
—
Programmable write protect
—
Supports FM and MFM modes
—
Supports Enhanced mode command for three-mode
Floppy Disk Drive (FDD)
—
Perpendicular recording drive support for 2.88 MB
—
Burst and Non-Burst modes
—
Full support for IBM Tape Drive Register (TDR) im-
plementation of AT and PS/2 drive types
—
16-byte FIFO
—
Error-free handling of data overrun and underrun
conditions during DMA transactions (i.e., does not
lose data or status bytes and is free of the NEC765A
bug)
—
Software compatible with the PC8477, which
contains a superset of the FDC functions in the
μ
DP8473, NEC
μ
PD765A/B and N82077
—
High-performance digital separator
—
Supports standard 5.25" and 3.5" FDDs
—
Supports up to four FDDs