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| 型號： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務(wù)器和工作站 |
| 文件頁數(shù)： | 168/257頁 |
| 文件大?。?/td> | 3163K |
| 代理商： | PC87413 |
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9.0 System Wake-Up Control (SWC)
(Continued)
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9.2.4
The SWC generates three system interrupts: IRQ (via SERIRQ), SMI (via SIOSMI) and SCI (via SIOSCI). The IRQ and SMI
interrupts are not related to the ACPI-compatible system control but are based on the external and internal events, each with
its status and enable bit in the SWC module. However, the status and enable bits for the GPIOE events (GPIOE10-17 and
GPIOE40-47) related to IRQ and SMI generation are located in the GPIO functional block (see Section 7.3 on page 137).
SCI is the Power Management interrupt defined by ACPI. Its status and enable bits are all located in the SWC module.
Interrupt Signals
IRQ Interrupt
The external and internal events processed by the SWC for IRQ generation set a status bit in the GPE1_STS_2 and
GPE1_STS_3 registers. Only those events that are allowed to be routed to the IRQ interrupt by the SWC have an associated
enable bit in the GPE1_2IRQ_LOW and GPE1_2IRQ_HIGH registers (see Sections 9.3.4 and 9.3.5 on pages181ff.). When
an enable bit is set, and if the corresponding status bit is set, an active IRQ is generated. The IRQ interrupt is independent
of the system sleep state.
SMI Interrupt
The external and internal events processed by the SWC for SMI generation set a status bit in the GPE1_STS_2 and
GPE1_STS_3 registers. Only those events that are allowed to be routed to the SMI interrupt by the SWC have an associated
enable bit in the GPE1_2SMI_LOW and GPE1_2SMI_HIGH registers (see Sections 9.3.6 and 9.3.7 on pages 183ff.). When
an enable bit is set, and if the corresponding status bit is set, an active SMI is generated. The SMI interrupt is independent
of the system sleep state.
SCI Interrupt
All external and internal events (including GPIOE) are exclusively processed by the SWC to generate the Power Manage-
ment interrupt, SCI. Each active event sets a status bit in the GPE1_STS_0 to GPE1_STS_3 registers. Three events, the
Power button event, the Sleep button event and the RTC event each have an additional status bit in the PM1b_STS_HIGH
register (PWRBTN_STS, SLPBTN_STS and RTC_STS bits, respectively). Each of the additional status bits is set only if the
PC8741x device is assigned the specific function by the ACPI software (see Sections 9.2.1 and 9.2.2 on pages 162ff.).
For each status bit, the SWC holds an enable bit in the GPE1_EN_0 to GPE1_EN_3 registers (see Sections 9.4.12 to 9.4.15
on pages 213ff.). A set status bit can cause the assertion of the SCI interrupt only when an enable bit is set. Each of the
three events mentioned in the previous paragraph also has additional enable bits in the PM1b_EN_HIGH register (see Sec-
tion 9.4.5 on page 207). Each additional enable and status bit is reset if the respective bit (PWRBTN_EV_DIS,
SLPBTN_EV_DIS or RTC_EV_DIS) in the ACPI_CFG register is reset (see Section 9.3.32 on page 201). This “dual control”
behavior is required for ACPI compatibility in case one of these events is implemented in an (optional) external ACPI con-
troller. An SCI from one of these dual control functions is generated if at least one enabled status bit (of the pair) is set.
The SCI interrupt is independent of the system sleep state with one exception
,
the Power button event. When the system is
in a sleep state (S1-S5), a set PWRBTN_STS bit generates an active SCI regardless of the value of the PWRBTN_EN bit.
S0 can be separated from the sleep states (S1-S5) only when the PC8741x device serves as an ACPI controller and the
software writes the system state (SLP_TYPx) in the PM1b_CNT_HIGH register. The bypass of the PWRBTN_EN bit during
sleep states (i.e., a set PWRBTN_STS bit generates SCI regardless of the PWRBTN_EN bit) is therefore available only if
the EXT_ST_SELECT bit in the SLP_ST_CFG register is reset (see Section 9.3.31 on page 200).
When the SCI interrupt is asserted and the system is in a sleep state (S1-S5), the WAK_STS bit of the PM1b_STS_HIGH
register is set. This feature, too, is available only if the EXT_ST_SELECT bit in the SLP_ST_CFG register is reset (the ACPI
controller is implemented by the PC8741x device).
Figure 49 shows the SCI generation by the dual control functions and the behavior of the Power button event as a function
of the sleep state.
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相關(guān)代理商/技術(shù)參數(shù) |
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| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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