- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365350 > PC87413 (National Semiconductor Corporation) LPC ServerI/O for Servers and Workstations PDF資料下載
參數(shù)資料
| 型號： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務(wù)器和工作站 |
| 文件頁數(shù)： | 138/257頁 |
| 文件大?。?/td> | 3163K |
| 代理商： | PC87413 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁當前第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁
7.0 General-Purpose Input/Output (GPIO) Ports
(Continued)
www.national.com
138
Revision1.2
P
Event Debounce Enable
The input signal can be debounced for about 15 msec before entering the detector. To ensure that the signal is stable, the
signal state is transferred to the event detector only after a debouncing period during which the signal has no transitions.
The debouncer adds a 16 msec delay to both assertion and de-assertion of the event pending indicator (IRQ, SMI, SCI).
The debounce is controlled by Event Debounce Enable (bit 6 of the GPCFG1 register).
Event Type and Polarity
Two trigger types of event detection are supported: edge and level. An edge event may be detected upon a source pin tran-
sition either from high to low or low to high. A level event may be detected when the source pin is either at high or low level.
The trigger type is determined by Event Type (bit 4 of the GPCFG1 register). The direction of the transition (for edge) or the
polarity of the active level (for level) is determined by Event Polarity (bit 5 of the GPCFG1 register).
The term
active edge
refers to a change in a GPIO pin level that matches the Event Polarity bit (1 for rising edge and 0 for
falling edge).
Active level
refers to the GPIO pin level that matches the Event Polarity bit (1 for high level and 0 for low level).
The corresponding bit of the GPEVST register is set by hardware whenever an active edge or an active level is detected
regardless of the GPEVEN register setting. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored.
A GPIO pin is in event pending state if an active event occurred (the corresponding bit of the GPEVST register is set) and
the corresponding bit of the GPEVEN register is set.
7.3.2
System notification on GPIO-triggered events is achieved by asserting at least one of the following output pins:
Interrupt Request (via the Interrupt Serializer in the LPC Bus Interface).
System Management Interrupt (SIOSMI, via the System Wake-Up Control).
The system notification for each GPIO pin is controlled by the corresponding bit in the GPEVEN register and the bits of the
GPEVR register. System notification by a GPIO pin is enabled if the corresponding bit of the GPEVEN register is set to 1.
The bits of the GPEVR register select the means of system notification (IRQ or SMI) that the detected GPIO event is routed
to. The event routing mechanism is described in Figure 38.
System Notification
Figure 38. GPIO Event Routing Mechanism for System Notification
The system notification to the target is asserted if at least one GPIO pin is in event pending state.
The selection of the target (the means of system notification) is determined by the GPEVR register. If IRQ is selected as one
of the means for the system notification, the specific IRQ number is determined by the IRQ selection procedure of the device
configuration. The assertion of IRQ (as a means of system notification) is disabled either when the GPIO functional block is
deactivated or when the V
DD
power is Off.
The assertion of SMI is independent of the activation of the GPIO functional block. SMI from GPIO pins connectedto a device
powered by V
DD
(VDDLOAD = 1 in the GPCFG2 register) is disabled when the V
DD
power is Off. However, SMI from GPIO
pins connected to a device powered by V
SB
(VDDLOAD = 0) is not affected by the status of the V
DD
power.
GPIO Event Pending Indication
SIOSMI
IRQ
Event
Routing
Logic
Enable
IRQ
Routing
Event Routing Register
(GPEVR)
Bit 1
Bit 0
Routed Events
from other GPIO Pins
Routing
Enable
SMI
GPIO Pin
GPIO Event to
GPIO Event to
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
| PC87415 | PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | PCI-IDE DMA Master Mode Interface Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。