
2003 National Semiconductor Corporation
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P
General Description
The National Semiconductor
PC8741x family of LPC Serv-
erI/O devices (“
PC8741x
”) comprises highly integrated Ad-
vanced I/O products. The PC8741x is targeted for a wide
rangeofserversandworkstationsthatusetheLowPinCount
(LPC) bus for the host interface and the serial ACCESS.bus
or SMBus
for the embedded controller interface.
The PC8741x features an X-Bus extension for read and write
operations over the X-Bus for both LPC and ACCESS.bus
cycles. Boot Flash and I/O devices can be accessed over this
X-Bus.
Embedded controllers can access the PC8741x and its X-Bus
via the ACCESS.bus or SMBus serial interface when V
SB
exists, regardless of the LPC bus state. Some of the
PC8741x logical devices can be disabled, or their pins can be
floated, under control of the V
SB
-powered serial bus.
The PC8741x provides a V
SB
-powered high-frequency clock
for on-chip peripherals and for other V
SB
-powered platform
components.
The PC8741x’s extended wake-up support complements the
chipset’s ACPI controller and the platform embedded control-
lers. The PC8741x can monitor the Power and Sleep buttons
and control the power supply of simple platforms that lack an
embedded controller. The System Wake-Up Control (SWC)
module is powered by V
SB
and V
BAT
power supplies. It sup-
ports flexible wake-up and power-off request mechanisms in
any sleep state. It features Main and Standby power-on
elapsed-time counters.
The PC8741x also incorporates a Floppy Disk Controller
(FDC), two serial ports (UARTs), a Keyboard and Mouse
Controller (KBC), a Real-Time Clock (RTC), a fully compliant
IEEE 1284 Parallel Port, General-Purpose Input/Output
(GPIO) for a total of 51 ports and an Interrupt Serializer for
Parallel IRQs.
Outstanding Features
I
LPC Interface, based on Intel’s
LPC Interface Specifi-
cation, Revision 1.0, September 29th, 1997
V
SB
-powered access to modules through ACCESS.bus
or SMBus (
PC87413 and PC87417
)
X-Bus Extension for memory and I/O (
PC87416 and
PC87417
)
PC01 Revision 0.5 and ACPI Revision 1.0b compliant
ServerI/O modules: Parallel Port, FDC, two Serial Ports
(UARTs) and a Keyboard and Mouse Controller (KBC)
Y2K-compliant RTC with 242 bytes of RAM
51 GPIO ports with a variety of wake-up events
Extremely low current consumption in Battery Backup mode
128-pin PQFP package
I
I
I
I
I
I
I
I
Block Diagram
PC87417
(See page 5 for other PC8741x diagrams.)
IEEE 1284
Parallel Port
Floppy Disk
Controller
Floppy Drive
Interface
Interface
LPC Bus
Interface
LPC
Interface
Serial
Port 1
Serial
Interface
Serial
IRQ
Parallel Port
Interface
V
DD
Serial
V
BAT
Keyboard &
Mouse Controller
Keyboard
Interface
Mouse
Interface
ServerI/O
Clock
I/O
Ports
GPIO
Ports
SMI
X-Bus
Extension
Wake-Up Control
System
SCI &
V
SB
ACCESS.bus
Interface
X-Bus
Interface
Power
Control
Wake-Up
Events
RTC
32.768 KHz
Clock
Generator
Low-F
Clock
Internal Clocks
XIRQ
Clock
Serial
Data
High-F
Clock
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Serial
Port 2
On
Power
Timers
Device
Configuration
July 2003
Revision 1.2
PC87413, PC87414, PC87416, PC87417
LPC ServerI/O for Servers and Workstations