
9.0 System Wake-Up Control (SWC)
(Continued)
Revision 1.2
173
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P
The RESUME_MD field in the PWONCTL register controls the behavior of the ONCTL and PWBTOUT signals during a Re-
sume from Power Fail condition (see Table 49 on page 189):
00b
The state of the ONCTL and PWBTOUT signals is controlled solely by the SLPS3 input generated by an (optional)
external ACPI controller.
If the sleep state control by SLPS3, SLPS5 option is selected by setting both the EXT_ST_SELECT bit in the
SLP_ST_CFG register and the EXTSTMUX bit in the SIOCF3 register to ‘1’, and if SLPS3 = 1 (no sleep), the V
DD
power
supply is turned on (ONCTL = 0). Otherwise, the V
DD
power supply remains off. Whenever ONCTL is asserted, a 100
ms pulse is also generated at the PWBTOUT output to inform an (optional) external ACPI controller of the new status of
the V
DD
power supply.
If the SLPS3, SLPS5 option is not selected (EXT_ST_SELECT bit in the SLP_ST_CFG register and EXTSTMUX bit in
the SIOCF3 register are both ‘0’), the V
DD
power supply remains off (“Silent mode”).
01b
The PC8741x device behaves the same as in the 00b combination.
In addition, if an RTC Alarm event was active during the Power Fail, the V
DD
power supply is turned on (ONCTL = 0) and
a 100 ms pulse is generated at the PWBTOUT output. This happens regardless of the setting of the EXT_ST_SELECT
and EXTSTMUX bits or of the value of the SLPS3 input.
10b
The state of the ONCTL and PWBTOUT signals is controlled solely by the LAST_ONCTL bit of the PWONCTL
register regardless of the setting of the EXT_ST_SELECT and EXTSTMUX bits.
If LAST_ONCTL = 1 (V
DD
power was on before Power Fail), the V
DD
power supply is turned on (ONCTL = 0) and a 100
ms pulse is generated at the PWBTOUT output. Otherwise, the V
DD
power supply remains off.
11b
The PC8741x device behaves the same as in the 10b combination.
In addition, if an RTC Alarm event was active during the Power Fail, the V
DD
power supply is turned on (ONCTL = 0) and
a 100 ms pulse is generated at the PWBTOUT output. This happens regardless of the value of the LAST_ONCTL bit of
the PWONCTL register.
The Resume from Power Fail function bypasses the regular control on the ONCTL and PWBTOUT signals.
After the Resume from Power Fail process ends, the ONCTL and PWBTOUT signals behave as described in Section 9.2.5
and in the
Power Button Override
and
Crowbar
sections (page 172).
9.2.7
The PC8741x devices support LED indicators for two purposes:
LED Control
G
Visual indication of the system power state or sleep state.
G
General-purpose visual indication of the software status.
The LEDCFG bit selects the configuration of the LED connection. There are two possible configurations: two regular LEDs
are connected between each pin and ground or V
SB
(one at LED1 and the other at LED2 pins) or one dual-color LED is
connected between the LED1 and LED2 pins. The LEDPOL bit selects the polarity of the On state at both pins (LED1 and
LED2). The LEDCFG and LEDPOL bits are located in the LEDCTL register (see Section 9.3.12 on page 190). The polarity
of the On state at LED1 and LED2 pins depends on the setting of the LEDCFG and LEDPOL bits (see Table ).
The LED1BLNK and LED2BLNK fields in the LEDBLNK register control the On/Off state or the blinking rate of the LED1 and
LED2 pins, respectively. For each LED pin, a different blink rate can be selected. Different blink rates can also be selected
for the dual-color LED mode (LEDCFG = 0).
The LEDMOD field in the LEDCTL register controls the behavior of the LED1 and LED2 pins in each power state or sleep
state (see Table 50 on page 190):
Table 42. LED On Polarity as a Function of LEDCFG and LEDPOL
LEDCFG
LEDPOL
LED1
LED2
Connection
0
0
High
Low
LED1 to LED2
0
1
Low
High
LED2 to LED1
1
0
High
High
LED1 and LED2 to GND
1
1
Low
Low
LED1 and LED2 to V
SB