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參數(shù)資料
| 型號： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務(wù)器和工作站 |
| 文件頁數(shù)： | 38/257頁 |
| 文件大小： | 3163K |
| 代理商： | PC87413 |
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38
Revision1.2
P
3.0
Device Architecture and Configuration
The PC8741x devices comprise a collection of legacy and proprietary functional blocks. Each functional block is described
in a separate chapter in this document. However, some parameters in the implementation of each functional block may vary
per ServerI/O device. This chapter describes the structure of the PC8741x devices and provides all logical device specific
information, including special implementation of generic blocks, system interface and device configuration.
3.1
The PC8741x consists of the following: up to 10 logical devices, the host interface, the system controller interface and a
central set of configuration registers. All these components are built around a central, internal bus. The internal bus is similar
to an 8-bit ISA bus protocol. See the Block Diagram on page 1, which illustrates the blocks and the internal bus.
The host, via the LPC Interface, can access the modules connected to the Internal bus. This interface supports 8-bit I/O
Read/Write, 8-bit Memory Read/Write and 8-bit DMA transactions of the LPC bus (see Section 4.2 on page 90).
The system controller can access these modules via the ACB Interface (
PC87413 and PC87417
). This interface supports
slave operation for 8-bit I/O Read/Write and 8-bit Memory Read/Write transactions of the ACCESS.bus (see Section 6.2 on
page 117).
Both the host and system controller accesses occur concurrently via the Internal bus.
The central configuration register set is ACPI compliant and supports PnP configuration. The configuration registers are struc-
tured as a subset of the Plug and Play Standard registers, defined in Appendix A of the
Plug and Play ISA Specification, Re-
vision 1.0a
by Intel and Microsoft
. All system resources assigned to the functional blocks (I/O address space, IRQ numbers
and DMA channels) are configured in and managed by the central configuration register set. In addition, some function-specific
parameters are configurable through the configuration registers and distributed to the functional blocks through special control
signals. Access through the ACB Interface (
PC87413 and PC87417
) ignores the PnP configuration registers and thus the
system resources assigned through them.
OVERVIEW
3.2
The configuration structure is comprised of a set of banked registers that are accessed via a pair of specialized registers.
CONFIGURATION STRUCTURE AND ACCESS
3.2.1
Access to the ServerI/O configuration registers is via an Index-Data register pair, using only two system I/O byte locations.
The base address of this register pair is determined during reset, according to the state of the hardware strapping option on
the BADDR pin. Table 8 shows the selected base addresses as a function of BADDR. The I/O location of the Index-Data
register pair is irrelevant when the configuration is accessed through the ACB Interface.
The Index-Data Register Pair
Table 8. BADDR Strapping Options
The Index register is an 8-bit read/write register located at the selected base address (Base+0). It is used as a pointer to the
configuration register file and holds the index of the configuration register that is currently accessible via the Data register.
Reading the Index register returns the last value written to it (or the default of 00h after reset).
The Data register is an 8-bit register (Base+1) used as a data path to any configuration register. Accessing the Data register
actually accesses the configuration register that is currently pointed to by the Index register.
The Index, Data and Logical Device Number registers are duplicated to enable concurrent access to the configuration reg-
isters from the LPC bus and ACCESS.bus, without contention (
PC87413 and PC87417
). Each bus has its own set of reg-
isters (Index/Data/LDN) powered from the V
well (ACCESS.bus set) or the V
well (LPC bus set). This power scheme
allows access to the configuration registers of the V
SB
-powered modules while in Power Off state (V
DD
off). In this case,
access is possible only through the ACCESS.bus.
BADDR
I/O Address
Index Register
Data Register
0
2Eh
2Fh
1
4Eh
4Fh
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
| PC87415 | PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | PCI-IDE DMA Master Mode Interface Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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