
9.0 System Wake-Up Control (SWC)
(Continued)
Revision 1.2
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P
9.4.2
This register contains the eight low bits of the PM1_STS register. The PC8741x devices contain the block ‘b’ instance of the
PM1_STS register. This register belongs to the PM1 Event Group of the ACPI fixed-feature space registers.
PM1_STS register bits that are specified by the ACPI but not implemented in the PC8741x devices have a ‘0’ value.
Power Well:V
SB
Location: Offset 00h
Type:
RO
PM1 Status Low Register (PM1b_STS_LOW)
9.4.3
This register contains the eight high bits of the PM1_STS register. The PC8741x devices contain the block ‘b’ instance of
the PM1_STS register. This register belongs to the PM1 Event Group of the ACPI fixed-feature space registers.
PM1_STS register bits that are specified by the ACPI but not implemented in the PC8741x devices have a ‘0’ value. All the
implemented status bits behave according to the Sticky Status Bit definition (the bit is set by the HIGH level of the hardware
signal and is only cleared by the software writing ‘1’ to it) in the ACPI Specification.
Power Well:V
SB
Location: Offset 01h
Type:
R/W1C
PM1 Status High Register (PM1b_STS_HIGH)
Bit
7
6
5
4
3
2
1
0
Name
Reserved
GBL_STS
BM_STS
Reserved
TMR_STS
Reset
0
0
0
0
0
0
0
0
Bit
Description
7-6
Reserved.
5
GBL_STS (Global Lock Status).
Not implemented. Always at ‘0’.
4
BM_STS (Bus Master Status).
Not implemented. Always at ‘0’.
3-1
Reserved.
0
TMR_STS (PM Timer Status).
Not implemented. Always at ‘0’.
Bit
7
6
5
4
3
2
1
0
Name
WAK_STS
Reserved
Ignored
RTC_STS
SLPBTN
_STS
PWRBTN
_STS
Reset
0
0
0
0
0
0
0
0
Bit
Description
7
WAK_STS (Wake-up Event Status).
Indicates that a power management event, enabled to generate SCI, has
occurred. This bit is set only if the system is in a sleep state (S1-S5). Writing ‘1’ while the system is in the
working state (S0), clears this bit; writing ‘0’ is ignored. When the system is in a sleep state (S1-S5) and an
enabled event is active, writing ‘1’ does not clear the WAK_STS bit.
0: Inactive (default)
1: At least one event enabled to SCI was active while the system was in a sleep state (S1-S5), since this bit was
last cleared
6-4
Reserved.
3
Ignored.
The data written is ignored; the data read is undefined.