
5.0 X-Bus Extension
(Continued)
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5.4.11
HAP0 and HAP1 registers hold the read/write protection and lock control bits for access control to XCS0 and XCS1, respec-
tively. Each register defines the access rights for a group of 16 blocks of the related chip select (see Section 5.3 on page 105
for more information on how to define these blocks). Each block is protected by three bits, which are accessed through the
block number written into the Host Access Protection Index field.
The lock bit for each block is cleared either by reset or by writing a ‘0’ through the ACCESS.bus (
PC87417
). When a lock
bit is cleared, the related write-protect flag is set and the read-protect flag is cleared.
Power Well:V
SB
Location:Offset 13h and 14h
Type:
Varies per bit
Host Access Protect Register (HAP0 to HAP1)
0
R/W or
RO
TRANSPD (X-Bus Transaction Speed).
When set to 1, removes the additional cycles from mode 0
read and write transactions. In this situation, the setting of WAITSEN bit in the XZCNF0 to XZCNF3
registers is ignored (wait states are disabled).
0: Sixteen additional CLK cycles (apart from the programmed number of wait states) are inserted into
mode 0 read and write transactions when accessing the XCSn (default)
1: No CLK cycles are inserted
Bit
7
6
5
4
3
2
1
0
Name
HAPINDX
INDXWR
LOCKXHP
HWRP
HRDP
Reset
0
0
0
0
0
0
1
0
Bit
Type
Description
7-4
R/W
HAPINDX (Host Access Protection Index).
Holds the index for the block number to be accessed by
the other fields in this register. All blocks are 16 KByte up to 1 MByte in size (see Section 5.3 on
page 105).
0000b - 1111b - index for block numbers of 0-15, respectively (0000b = default).
INDXWR (Index Write).
Indicates an index write transaction for which the value of bits 2-0 are ignored
(not written). This bit always returns ‘0’ when read.
0: Index and Data write transaction (writes bits 2-0 according to the newly written index); (default)
1: Index update write transaction (bits 2-0 are not updated by this write)
R/W1S
LOCKXHP (Lock Host Protection).
When set to ‘1’ through the LPC bus, this bit locks itself and the
two HWRP and HRDP protection bits by disabling writing to them. The block number these three bits
relate to is pointed to by the Index field. Once set, this bit can be cleared either by the V
DD
Power-Up
reset (or Hardware reset) or by the V
SB
Power-Up reset, according to the VSBLOCK bit in the
ACBLKCTL register (see Section 6.3.4 on page 128). In addition, this bit is cleared by setting the
UNLOCKX bit in the ACBLKCTL register (
PC87417
).
This bit may be set or reset through the ACCESS.bus (
PC87417
), regardless of its value (it is not self-
locking).
0: Changes to protection bits (2-0) for this block are enabled (default)
1: Protection bits (2-0) for this block are locked and their values cannot be changed
R/W or
RO
erasing of the flash memory connected to the XCSn. The block number affected by this field is the one
pointed to by the Index field.
0: Host writes to this block are allowed
1: Host writes to this block are inhibited (default)
R/W or
RO
flash memory connected to the XCSn. The block number affected by this field is the one pointed to by
the Index field.
0: Host reads from this block are allowed (default)
1: Host reads from this block are inhibited
3
WO
2
1
HWRP (Host Write Protection).
This bit prevents writes to a block, thus preventing programming or
0
HRDP (Host Read Protection).
This bit prevents reads from a block, thus protecting the contents of the
Bit
Type
Description