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參數(shù)資料
| 型號： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務(wù)器和工作站 |
| 文件頁數(shù)： | 43/257頁 |
| 文件大?。?/td> | 3163K |
| 代理商： | PC87413 |
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3.0 Device Architecture and Configuration
(Continued)
Revision 1.2
43
www.national.com
P
Control
The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate
register controls the activation of the associated functional block. Activation enables access to the functional block’s runtime
registers and attaches its system resources, which are unassigned as long as it is not activated. Other effects may apply on
a function-specific basis (such as clock enable and active pinout signaling). Access to the configuration register of the logical
device is enabled even when the logical device is not activated.
Standard Configuration
The standard configuration registers manage the PnP resource allocation to the functional blocks. The I/O port base address
descriptor 0 is a pair of registers at Index 60-61h that hold the first 16-bit base address for the register set of the functional
block. An optional 16-bit second base-address (descriptor 1) at index 62-63h is used for logical devices with more than one
continuous register set. Interrupt Number and Wake-Up on IRQ Enable (index 70h) and IRQ Type Select (index 71h) allocate
an IRQ line to the block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where
applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable.
Special Configuration
The vendor-defined registers, starting at index F0h, control function-specific parameters such as operation modes, power
saving modes, pin TRI-STATE, clock rate selection and non-standard extensions to generic functions.
3.2.5
The default configuration setup of the PC8741x device is determined by the six reset types described in Section 2.2 on
page 34. See the specific register descriptions for the bits affected by each reset source.
In the event of a V
DD
Power-Up (also induced by V
SB
Power-Up reset) or Hardware reset, the PC8741x device wakes up
with the following default configuration setup:
The configuration base address is 2Eh or 4Eh, according to the BADDR strap pin value, as shown in Table 8 on page 38.
If the VSBLOCK bit in the ACBLKCTL register is ‘0’ (see Section 6.3.4 on page 128; in
PC87414 and PC87416
,
VSBLOCK is always ‘0’), all lock bits in the Configuration Control registers are reset (the protected bits are unlocked).
All the actions performed by the Host Software reset are executed.
If a Host software reset occurs, the PC8741x device wakes up with the following default configuration setup:
All logical devices are disabled (the Activation bit is reset) and the V
SB
-powered logical devices (X-Bus, GPIO, RTC and
SWC) remain functional but their registers cannot be accessed by the Host.
Standard configuration registers of all logical devices are set to their default values.
National proprietary functions are not assigned with any default resources and the default values of their base addresses
are all 00h.
All Legacy devices are reset. Default values are loaded into the Legacy module runtime registers.
Default Configuration Setup
3.3
Module control is performed primarily through the Activation bit (bit 0 of index 30h) of each logical device. The operation of
each module can be controlled either by the host through the LPC bus or by the Embedded Controller through the
ACCESS.bus (
PC87413 and PC87417
). This dual control is supported by two interacting mechanisms: a dual enable/dis-
able and an access lock (the access lock is available only through the ACCESS.bus).
MODULE CONTROL
3.3.1
Module Enable/Disable
LPC Control.
Module enable/disable by the host through the LPC bus is controlled by the following bits (see Figure 5 on
page 45):
G
Activation bit (bit 0) in index 30h of the Standard configuration registers (see Section 3.2.3 on page 40).
G
Fast Disable bit in the SIOCF6 register (see Section 3.7.7 on page 54) - only for the FDC, Parallel Port and Serial
Port 1 and 2 modules.
G
Fast Disable bit in the SWCFDIS register (see Section 9.3.8 on page 185) - only for the KBC, FDC, Parallel Port and
Serial Port 1 and 2 modules.
G
Global Enable bit (GLOBEN) in the SIOCF1 register (see Section 3.7.2 on page 49).
A module is enabled only if all these bits are set to their “enable” value and the module’s enable/disable is not controlled by
the Embedded Controller as described in the next paragraph. Although possible, changing the above bits by the Embedded
Controller through the ACCESS.bus (
PC87413 and PC87417
) is not recommended.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
| PC87415 | PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | PCI-IDE DMA Master Mode Interface Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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