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參數資料
| 型號： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務器和工作站 |
| 文件頁數： | 172/257頁 |
| 文件大?。?/td> | 3163K |
| 代理商： | PC87413 |
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9.0 System Wake-Up Control (SWC)
(Continued)
www.national.com
172
Revision1.2
P
9.2.6
Three special Power Management functions are provided by the PC8741x device to respond to abnormal system behavior.
These are:
Special Power Management Functions
G
Power Button Override, which forces the V
DD
power supply to be turned off when the software does not respond to
the SCI interrupt.
G
Crowbar, which forces the ONCTL to release the On request, thus protecting an overloaded V
DD
power supply that
refuses to turn on.
G
Resume from Power Fail, which enables a system to return to a predetermined state when returning from Power Fail
(caused by the mechanical switch or by AC power failure).
These functions bypass the mechanisms described in Section 9.2.5 and thus directly control the ONCTL and PWBTOUT
outputs.
Power Button Override
Whenever the Power button (PWBTIN) is pressed continuously for more than 3.9 seconds, the PC8741x device detects a
Power Button Override condition. The Power button pressing at PWBTIN is replicated at PWBTOUT during these 3.9 sec-
onds. PWBTOUT is then forced active for 0.2 seconds regardless of the actual level at PWBTIN. Thus, the pulse generated
at PWBTOUT has a width of minimum 4.1 seconds, allowing an (optional) external ACPI controller to detect this Power But-
ton Override condition. In addition, at the end of the 4.1 seconds, ONCTL is forced to inactive level (V
DD
power supply Off).
A Power Button Override condition also resets the PWRBTN_STS bit in the PM1b_STS_HIGH register (set by the Power
button event) and updates the current sleep state of the PC8741x device to S45 (since the software is not capable of doing
it). In addition, it sets the PWR_OVR_STS bit in the SWC_CTL register.
This function bypasses the regular control on the ONCTL and PWBTOUT signals (see Figures 50 and 51).
After a Power Button Override condition, only an active Power button event is allowed to wake-up the system (by setting
ONCTL = 0 and generating a PWBTOUT pulse). However, in order to protect the power supply, ONCTL can go active
(ONCTL = 0) only 1 second after the power supply has been turned off (by setting ONCTL = 1).
In Legacy Power Button mode, when the V
DD
power is on, pressing the Power button (PWBTIN) forces ONCTL to inactive
level (V
DD
power supply Off) before a Power Button Override condition is detected. In this case, the PWR_OVR_STS bit is
not set.
Crowbar
When a valid wake-up event or a high SLPS3 signal activates the V
DD
power supply (by setting ONCTL = 0), the PC8741x
device starts checking the presence of the V
DD
power. If the V
DD
power fails to resume for a time period longer than the
Crowbar timeout, the power-on request is aborted (by setting ONCTL = 1). Crowbar timeout is also started if the V
DD
power
falls while the V
DD
power supply is On (ONCTL = 0). If the V
DD
power fails to resume before the timeout period expired, the
V
DD
power supply is turned off (by setting ONCTL = 1).
After turning the V
DD
power supply Off (by setting ONCTL = 1), a 4 sec pulse is generated at the PWBTOUT output. This
pulse informs an (optional) external ACPI controller of the occurrence of the Crowbar timeout by simulating a Power Button
Override condition.
This function bypasses the regular control of the ONCTL and PWBTOUT signals (see Figures 50 and 51).
The Crowbar timeout value is selected by the CRBAR_TOUT field in the PWONCTL register (see Section 9.3.11 on
page 188). The equivalent timeout is in the range of 0.5 to 20 seconds (the default value is 20 seconds).
When a Crowbar event is detected, the CROWBAR_STS bit in the SWC_CTL register (see Section 9.3.10 on page 187) is
set.
Only an active Power button event is allowed to retry the activation of the V
DD
power supply (by setting ONCTL = 0). However,
no retry can take place for 5 seconds after the V
DD
power supply was turned off (by setting ONCTL = 1) because all wake-
up events (including Power button) are disabled for 1 second after the end of the PWBTOUT pulse.
Resume from Power Fail
Whenever a Power Fail condition is detected (i.e., when V
DD
and V
SB
power supplies are off), the value of the ONCTL signal
is saved in the LAST_ONCTL bit of the PWONCTL register (see Section 9.3.11 on page 188). When the system exits Power
Fail (i.e., when V
SB
power is back on), this read-only bit serves as a snapshot of the V
DD
power supply status before the
power was turned off (by an external agent, such as a mechanical switch).
The WAS_PFAIL bit in the PWONCTL register is set by V
SB
Power-Up reset (the system exits Power Fail), thus indicating
that a Resume from Power Fail condition occurred. This indication is used by the software to decide if the system woke up
from Power Fail or from a sleep state.
The Resume from Power Fail process starts 1 second after the V
SB
power is on. This prevents the selection of an erroneous
current sleep state during V
SB
power-On transitions.
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| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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