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參數(shù)資料
| 型號： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務器和工作站 |
| 文件頁數(shù)： | 44/257頁 |
| 文件大?。?/td> | 3163K |
| 代理商： | PC87413 |
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3.0 Device Architecture and Configuration
(Continued)
www.national.com
44
Revision1.2
P
ACCESS.bus Control.
Module enable/disable by the Embedded Controller through the ACCESS.bus (
PC87413 and
PC87417
) is controlled by the following bits:
G
Access lock bit (
xxx
ALOK) in the ACCLCF1 and ACCLCF2 registers (see Sections 6.3.7 and 6.3.8 on pages 132ff.)
- for the FDC, Parallel Port, Serial Port 1 and 2, KBC, X-Bus, RTC and SWC modules.
G
Fast Disable bit in the ACBFDIS register (see Section 6.3.5 on page 130) - only for the KBC, FDC, Parallel Port and
Serial Port 1 and 2 modules.
A module is enabled if both the Access lock bit is set to “l(fā)ock” and the Fast Disable bit is set to “enable”. When the module
enable/disable is controlled by the Embedded Controller, the setting of the Activation, Fast Disable (in both SIOCF6 and
SWCFDIS) or Global Enable bits is ignored (see Figure 5 on page 45).
When a V
DD
-powered module (FDC, Parallel Port and Serial Port 1 and 2 and KBC) is disabled, the following takes place:
G
The host system resources of the logical device (IRQ, DMA and runtime address range) are unassigned.
G
Access to the standard- and device-specific Logical Device configuration registers, through LPC bus or ACCESS.bus,
remains enabled.
G
Access to the module’s runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is
not generated).
G
Access to the module’s runtime registers through the ACCESS.bus causes unpredictable results, and therefore is not
allowed.
The module’s internal clock is disabled (the module is not functional) to lower power consumption.
When a V
SB
-powered module (X-Bus, GPIO, RTC and SWC) is disabled, the following takes place:
G
The host system resources of the logical device (IRQ, DMA and runtime address range)) are unassigned, with the
exception of the XIRQ interrupt, which is not a resource of the X-Bus Extension and therefore remains operational.
G
Access to the standard and device specific Logical Device configuration registers, through the LPC bus or
ACCESS.bus, remains enabled.
G
Access to the module’s runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is
not generated).
G
Access to the module’s runtime registers through the ACCESS.bus causes unpredictable results, and therefore is not
allowed.
The module is functional.
3.3.2
A module can be locked to allow only ACCESS.bus control over its registers. In this case, only the setting of the Fast Disable
bit in the ACBFDIS register controls the enable/disable of the module (see Figure 5 on page 45). The setting of the Activation,
Fast Disable (in both SIOCF6 and SWCFDIS) or Global Enable bits is ignored. Module locking is controlled by the bits of
the ACCLCF1 and ACCLCF2 registers (see Sections 6.3.7 and 6.3.8 on pages 132ff.).
When a module is locked for sole use by ACCESS.bus, the following takes place:
Module Lock by ACCESS.bus (PC87413 and PC87417)
G
The system resources of the logical device (IRQ, DMA) are forced to their inactive level, with the exception of the
XIRQ interrupt, which is not a resource of the X-Bus Extension and therefore remains operational.
G
Host read access to the Logical Device Standard and Device Specific configuration registers (through the LPC bus)
remains enabled. Host write access to these registers is ignored.
G
Host access to the module’s runtime registers (through the LPC bus) is disabled and the transaction is performed ac-
cording to the setting of the ACCLMD field, as described in the next paragraph.
The module is functional.
If, the host tries to access the runtime registers of a locked module, the LPC transaction is performed according to the value
of the ACCLMD field in the ACBCFG register (see Section 6.3.3 on page 128). In addition, the ACCLVIOL bit in the ACBCST
register (see Section 6.3.2 on page 127) is set, indicating a lock violation attempt.
Since a locked module and a disabled module behave similarly, the ACTSTAT bit in the ACBCFG register (see Section 6.3.3
on page 128) allows the software to control the behavior of the Activation bit when read through the LPC bus. When a mod-
ule is locked or disabled by the Fast Disable bit in the ACBFDIS register, the ACTSTAT bit selects the value the host reads
from the Activation bit. This value is either the actual value of the Activation bit or ‘0’ (module disabled).
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PDF描述 |
|---|---|
| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
| PC87415 | PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | PCI-IDE DMA Master Mode Interface Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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