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參數(shù)資料
| 型號： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務(wù)器和工作站 |
| 文件頁數(shù)： | 167/257頁 |
| 文件大?。?/td> | 3163K |
| 代理商： | PC87413 |
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9.0 System Wake-Up Control (SWC)
(Continued)
Revision 1.2
167
www.national.com
P
Software Power On/Off Events
A Software Power event is triggered when software writes ‘1’ to the SW_ON_CTL bit (for Power On) or to the SW_OFF_CTL
bit (for Power Off). After being written ‘1’, these bits automatically return to their default value of ‘0’. Both bits are located in
the SWC_CTL register (see Section 9.3.10 on page 187). If the V
DD
power is not preset, these two bits can be written ‘1’
through the ACCESS.bus (
PC87413 and PC87417
), which is powered by V
SB
.
A Software Power On event sets the SW_ON_STS status bit and a Software Power Off event sets the SW_OFF_STS status
bit. Both bits are in the GPE1_STS_3 register (see Section 9.4.11 on page 211). A status bit is cleared only when the soft-
ware writes ‘1’ to it.
9.2.3
Compliance with
ACPI Specification, Revision 1.0b, Feb. 2, 1999
requires the PC8741x devices to recognize the six system
states: Working (G0/S0), Sleeping (G1-S1 to G1-S4) and Soft-off (G2/S5). The system state is written by the host into the
SLP_TYPx field of the PM1b_CNT_HIGH register (see Section 9.4.7 on page 208) and updated by writing a ‘1’ to the
SLP_EN bit in the same register.
The value written in the SLP_TYPx field is translated to one of the internal states (S0 to S5), using the data programmed in
the Sleep Type Encoding registers. This translation mechanism allows the software to use any SLP_TYPx encoding scheme.
Each of the six Sleep Type Encoding registers (S0_SLP_TYP to S5_SLP_TYP; see Section 9.3.30 on page 199) contains
a 3-bit SLP_ENC_TYP field. The software must program this field with the SLP_TYPx code used for the internal state rep-
resented by the register. The software must program all six registers even if not all the system states are supported.
The SWC uses three current sleep states to control its operation. The six decoded internal states are converted to the current
sleep states as follows (see Section 9.2.5 for the usage of the current sleep states):
Sleep States
G
S0, S1 and S2 are converted to the S12 current state; this is the active state for the PC8741x device, with V
DD
and
V
SB
power supplies being On.
G
S3 is converted to the S3I current state; in this sleep state, the V
SB
power is On but the V
DD
power supply can be
On or Off, according to the setting of the S3I_VDD_ON bit in the SLP_ST_CFG register (see Section 9.3.31 on
page 200).
G
S4 is converted to either S3I or S45 current states, according to the setting of the S4_SELECT bit in the
SLP_ST_CFG register (see Section 9.3.31 on page 200).
G
S5 is converted to the S45 current state; in this sleep state, the V
SB
power is On but the V
DD
power supply is Off.
If an active (optional) ACPI controller is located in an external device, the SLPS3 and SLPS5 signals are used to determine
the system sleep state. This option is selected by setting both the EXTSTMUX bit in the SIOCF3 register (see Section 3.7.4
on page 51) and the EXT_ST_SELECT bit in the SLP_ST_CFG register (see Section 9.3.31 on page 200) to ‘1’. Table 41
shows how the levels of the SLPS3 and SLPS5 signals are converted to current sleep states.
Note
: The internal and external sleep state modes are mutually exclusive. The internal sleep state register
(PM1b_CNT_HIGH) should not be used when External Sleep State mode is selected. Similarly, pins SLPS3 and SLPS5
should not be used when Internal Sleep State mode is selected.
The use of the external SLPS3 and SLPS5 signals to determine the current sleep state is enabled 1 second after the V
SB
power is on. This prevents the selection of an erroneous current sleep state during V
SB
power-On transitions.
In Legacy Power Button mode, when the V
DD
power is on, an S45 current state is generated by a low-level signal at
PWBTIN.
Table 41. SLPS3, SLPS5 Conversion to Current Sleep States
SLPS3
SLPS5
Current Sleep State
1
1
S12
0
1
S3I
0
0
S45
1
0
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
| PC87415 | PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | PCI-IDE DMA Master Mode Interface Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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