參數(shù)資料
型號: PC87413
廠商: National Semiconductor Corporation
英文描述: LPC ServerI/O for Servers and Workstations
中文描述: LPC ServerI /服務器和工作站
文件頁數(shù): 212/257頁
文件大?。?/td> 3163K
代理商: PC87413
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁當前第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁
9.0 System Wake-Up Control (SWC)
(Continued)
www.national.com
212
Revision1.2
P
Bit
Description
7
SW_OFF_STS (Software Off Event Status).
Indicates that the software wrote a ‘1’ to the SW_OFF_CTL bit in
the SWC_CTL register to request a V
DD
power off sequence. Writing ‘1’ clears this bit; writing ‘0’ is ignored.
0: Inactive since last cleared (default)
1: ‘1’ was written to the SW_OFF_CTL bit in the SWC_CTL register
6
SW_ON_STS (Software On Event Status).
Indicates that the software wrote a ‘1’ to the SW_ON_CTL bit in the
SWC_CTL register to request a V
DD
Power On sequence. When the V
DD
power is off, the SW_ON_CTL bit can
be written only through the ACCESS.bus (
PC87413 and PC87417
). Writing ‘1’ clears this bit; writing ‘0’ is
ignored.
0: Inactive since last cleared (default)
1: ‘1’ was written to the SW_ON_CTL bit in the SWC_CTL register
5
WDO_EVT_STS (Watchdog Event Status).
Indicates that watchdog time-out has occurred. Writing ‘1’ clears
this bit; writing ‘0’ is ignored.
0: Inactive (default)
1: A watchdog time-out has occurred
4
MOD_IRQ_STS (Modules IRQ Event Status).
Indicates that an IRQ was generated by one of the Legacy
modules (FDC, Parallel Port, Serial Port 1 and 2) or by the XIRQ pin (
PC87416 and PC87417
). For Legacy
modules IRQ, this bit is set only if the IRQ is enabled for wake-up (bit 4 of the Standard configuration register
at index 70h) and the related module is active (see Section 3.2.3 on page 40). For the XIRQ pin, this bit is set
only if XIRQ is enabled for wake-up by setting both the IRQEN and the PWUREN bits in the XIRQC register
(see Section 5.4.4 on page 110) to ‘1’. Writing ‘1’ clears this bit; writing ‘0’ is ignored.
0: Inactive since last cleared (default)
1: An enabled IRQ, from one of the Legacy modules or from the XIRQ pin, is active
3
MS_IRQ_STS (Mouse IRQ Event Status).
Indicates that an IRQ was generated by the mouse interface section
of the KBC module. This bit is set only if the IRQ is enabled for wake-up (bit 4 of the Mouse Logical Device
configuration register at index 70h) and the KBC module is active (see Section 3.2.3 on page 40). Writing ‘1’
clears this bit; writing ‘0’ is ignored.
0: Inactive since last cleared (default)
1: An enabled IRQ, from the mouse interface section of the KBC module, is active
2
KBD_IRQ_STS (Keyboard IRQ Event Status).
Indicates that an IRQ was generated by the keyboard interface
section of the KBC module. This bit is set only if the IRQ is enabled for wake-up (bit 4 of the Keyboard Logical
Device configuration register at index 70h) and the KBC module is active (see Section 3.2.3 on page 40). Writing
‘1’ clears this bit; writing ‘0’ is ignored.
0: Inactive since last cleared (default)
1: An enabled IRQ, from the keyboard interface section of the KBC module, is active
1
P12_EVT_STS (Port P12 Event Status).
Indicates that an active high signal was generated by the KBC
module, at the P12 pin. This bit is set only if the KBC module is active (see Section 3.2.3 on page 40). Writing
‘1’ clears this bit; writing ‘0’ is ignored.
0: Inactive since last cleared (default)
1: An active high signal at the P12 pin was generated by the KBC module
0
RTC_EVT_STS (RTC Alarm Event Status).
Indicates that an enabled RTC alarm has occurred. This bit is
similar to the RTC_STS bit in the PM1b_STS_HIGH register. Writing ‘1’ clears this bit and the RTC_STS bit in
the PM1b_STS_HIGH register; writing ‘0’ is ignored.
0: Inactive (default)
1: An RTC alarm has occurred
相關PDF資料
PDF描述
PC87414 LPC ServerI/O for Servers and Workstations
PC87416 LPC ServerI/O for Servers and Workstations
PC87417 LPC ServerI/O for Servers and Workstations
PC87415 PCI-IDE DMA Master Mode Interface Controller
PC87415VCG PCI-IDE DMA Master Mode Interface Controller
相關代理商/技術參數(shù)
參數(shù)描述
PC87414 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations
PC87415 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller
PC87415VCG 制造商:Rochester Electronics LLC 功能描述:- Bulk
PC87416 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations
PC87417 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations