
9.0 System Wake-Up Control (SWC)
(Continued)
www.national.com
212
Revision1.2
P
Bit
Description
7
SW_OFF_STS (Software Off Event Status).
Indicates that the software wrote a ‘1’ to the SW_OFF_CTL bit in
the SWC_CTL register to request a V
DD
power off sequence. Writing ‘1’ clears this bit; writing ‘0’ is ignored.
0: Inactive since last cleared (default)
1: ‘1’ was written to the SW_OFF_CTL bit in the SWC_CTL register
6
SW_ON_STS (Software On Event Status).
Indicates that the software wrote a ‘1’ to the SW_ON_CTL bit in the
SWC_CTL register to request a V
DD
Power On sequence. When the V
DD
power is off, the SW_ON_CTL bit can
be written only through the ACCESS.bus (
PC87413 and PC87417
). Writing ‘1’ clears this bit; writing ‘0’ is
ignored.
0: Inactive since last cleared (default)
1: ‘1’ was written to the SW_ON_CTL bit in the SWC_CTL register
5
WDO_EVT_STS (Watchdog Event Status).
Indicates that watchdog time-out has occurred. Writing ‘1’ clears
this bit; writing ‘0’ is ignored.
0: Inactive (default)
1: A watchdog time-out has occurred
4
MOD_IRQ_STS (Modules IRQ Event Status).
Indicates that an IRQ was generated by one of the Legacy
modules (FDC, Parallel Port, Serial Port 1 and 2) or by the XIRQ pin (
PC87416 and PC87417
). For Legacy
modules IRQ, this bit is set only if the IRQ is enabled for wake-up (bit 4 of the Standard configuration register
at index 70h) and the related module is active (see Section 3.2.3 on page 40). For the XIRQ pin, this bit is set
only if XIRQ is enabled for wake-up by setting both the IRQEN and the PWUREN bits in the XIRQC register
(see Section 5.4.4 on page 110) to ‘1’. Writing ‘1’ clears this bit; writing ‘0’ is ignored.
0: Inactive since last cleared (default)
1: An enabled IRQ, from one of the Legacy modules or from the XIRQ pin, is active
3
MS_IRQ_STS (Mouse IRQ Event Status).
Indicates that an IRQ was generated by the mouse interface section
of the KBC module. This bit is set only if the IRQ is enabled for wake-up (bit 4 of the Mouse Logical Device
configuration register at index 70h) and the KBC module is active (see Section 3.2.3 on page 40). Writing ‘1’
clears this bit; writing ‘0’ is ignored.
0: Inactive since last cleared (default)
1: An enabled IRQ, from the mouse interface section of the KBC module, is active
2
KBD_IRQ_STS (Keyboard IRQ Event Status).
Indicates that an IRQ was generated by the keyboard interface
section of the KBC module. This bit is set only if the IRQ is enabled for wake-up (bit 4 of the Keyboard Logical
Device configuration register at index 70h) and the KBC module is active (see Section 3.2.3 on page 40). Writing
‘1’ clears this bit; writing ‘0’ is ignored.
0: Inactive since last cleared (default)
1: An enabled IRQ, from the keyboard interface section of the KBC module, is active
1
P12_EVT_STS (Port P12 Event Status).
Indicates that an active high signal was generated by the KBC
module, at the P12 pin. This bit is set only if the KBC module is active (see Section 3.2.3 on page 40). Writing
‘1’ clears this bit; writing ‘0’ is ignored.
0: Inactive since last cleared (default)
1: An active high signal at the P12 pin was generated by the KBC module
0
RTC_EVT_STS (RTC Alarm Event Status).
Indicates that an enabled RTC alarm has occurred. This bit is
similar to the RTC_STS bit in the PM1b_STS_HIGH register. Writing ‘1’ clears this bit and the RTC_STS bit in
the PM1b_STS_HIGH register; writing ‘0’ is ignored.
0: Inactive (default)
1: An RTC alarm has occurred