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參數(shù)資料
| 型號： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務(wù)器和工作站 |
| 文件頁數(shù)： | 34/257頁 |
| 文件大?。?/td> | 3163K |
| 代理商： | PC87413 |
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2.0 Power, Reset and Clocks
(Continued)
www.national.com
34
Revision1.2
P
2.2
The PC8741x devices have up to six reset sources:
V
PP
Power-Up Reset
- activated when either V
SB
or V
BAT
is powered up after both have been off.
V
SB
Power-Up Reset
- activated when V
SB
is powered up.
V
DD
Power-Up Reset
- activated when V
DD
is powered up.
Hardware Reset
- activated when the LRESET input is asserted (low).
Host Software Reset
- triggered by the HSWRST bit of the SIOCF1 register (see Section 3.7.2 on page 49); the
HSWRST bit is set by the host through the LPC Interface.
Controller Software Reset (PC87413 and PC87417)
- triggered by the CSWRST bit of the ACBCFG register (see Sec-
tion 6.3.3 on page 128); the CSWRST bit is set by the system controller through the ACCESS.bus Interface.
Unless otherwise noted, reset references throughout the modules of the PC8741x devices default to the following resets:
RESET SOURCES AND TYPES
G
For V
PP
-retained functions (RTC, part of SWC and some other functions): V
PP
Power-Up reset.
G
For V
SB
-powered functions (ACCESS.bus, X-Bus, GPIO ports, Clock Generator, part of SWC and part of Configura-
tion Control): V
SB
Power-Up reset or Controller Software Reset (within the limitations described in Section 2.2.3).
G
For V
DD
-powered functions (Legacy modules, LPC and part of Configuration Control): V
DD
Power-Up reset,
Hardware Reset or Host Software Reset (within the limitations described in Section 2.2.6).
The following sections detail the sources and effects of the various resets on the PC8741x devices per reset source.
2.2.1
V
PP
is an internal power signal derived from V
SB
and V
BAT
. V
PP
Power-Up reset is generated by an internal circuit that de-
tects the status of the V
PP
power. An active V
PP
Power-Up reset signal is generated following a rise in the V
PP
until the V
PP
power within the accepted range is detected (see Section 11.1.5 on page 232). When V
PP
Power-Up reset is active, it resets
the modules and registers whose values are retained by V
PP
(RTC, part of SWC and some other functions). The V
PP
Power-
Up reset also activates the 32 KHz internal crystal oscillator.
V
PP
Power-Up Reset
2.2.2
V
SB
Power-Up reset is generated by an internal circuit when V
SB
power is applied. This reset is completed after 8,192 cycles
of the 32 KHz clock (t
32KOSC
). However, if the 32 KHz on-chip crystal oscillator was disabled before V
SB
power-up, a delay
of t
32KW
(see
Low Frequency Clock Timing
on page 242) is added to t
IRST
(see
VSB Power-Up Reset
on page 239) to ac-
count for the time required by the 32 KHz oscillator to stabilize. In addition, if the Hardware reset (LRESET) is de-asserted
in an early stage, only 1,280 clock cycles are required to complete the V
SB
Power-Up reset.
External devices should wait at least t
IRST
before accessing the PC8741x device. However, if the system controller accesses
the PC8741x device (through the ACCESS.bus) before t
IRST
ends, both the ACBDAT and the ACBCLK signals will float until
the end of V
SB
Power-Up reset, which is when the ACCESS.bus Interface becomes operational. Since these signals are
pulled-up by external resistors, this situation is equivalent to generating a NACK condition in response to the system con-
troller access (see Section 6.2.4 on page 118).
V
SB
Power-Up reset performs the following actions and all the actions performed by V
DD
Power-Up reset (if the V
DD
power
is already active):
Activates the Clock Generator and sets its output to the default frequency.
Puts pins with V
SB
strap options into TRI-STATE and enables their internal pull-down resistors.
Samples the logic levels of the V
SB
strap pins.
Sets up the PC8741x device slave address on the ACCESS.bus (
PC87413 and PC87417
).
Resets the V
SB
-powered lock bits in the Configuration Control and X-Bus (
PC87416 and PC87417
).
Loads default values to the GPIO Configuration bits: VDDLOAD and BUSCTL.
Loads default values to the V
SB
-powered bits in SWC.
Loads default values to the bits in ACCESS.bus Interface (
PC87413 and PC87417
).
Sets up the pull-up option and the default source for the V
SB
-powered multiplexed output pins.
ExecutesalltheactionsperformedbytheControllerSoftwarereset(seeSection2.2.3onpage 35)in
allPC8741xdevices
.
V
SB
Power-Up Reset
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| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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