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參數(shù)資料
| 型號： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務(wù)器和工作站 |
| 文件頁數(shù)： | 119/257頁 |
| 文件大?。?/td> | 3163K |
| 代理商： | PC87413 |
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6.0 ACCESS.bus Interface
(Continued)
Revision 1.2
119
www.national.com
P
6.2.5
According to this rule, the master generates an acknowledge clock pulse after each byte transfer and the receiver (master
or slave) sends an acknowledge signal after every byte received. There are two exceptions to this rule:
When the master is the receiver, it must indicate to the slave transmitter the end of the expected data by not acknowl-
edging (NACK) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock
pulse (generated by the master), but the ACBDAT line is not pulled down.
When a problem has occurred in the slave receiver, it sends a NACK to indicate that it did not accept the previous data
byte or cannot accept additional data bytes.
The NACK indicates an error in data reception (by slave or master) and a request to repeat the ACCESS.bus transaction.
Acknowledge after Every Byte Rule
6.2.6
Each device on the bus has a unique address. The PC8741x device starts a slave address set-up process if one of the fol-
lowing occurs:
A V
SB
Power-Up reset is activated by V
SB
going up: in this case, the ACBSA strap value is also sampled (see Section
2.2.2 on page 34).
A broadcast transaction to the General Call address with a “Reset and write programmable part of slave address by hard-
ware” command is received over the ACCESS.bus (see below).
During the slave address set-up process, the PC8741x device performs the following actions in the order listed:
1. Checks the value of the ACBSADD field in the ACBCF register (see Section 3.7.11 on page 57); if the value of the bits
is valid (not zero), the value is adopted and the other two actions are ignored.
2. Checks the value of the ACBSA strap sampled at the V
SB
Power-Up reset.
3. Adopts one of the two fixed values (see Section 1.4.11 on page 29) for its slave address, according to the ACBSA value.
Before any data is transmitted, the master transmits the address of the target slave. The slave must send an acknowledge
signal on the ACBDAT line once it recognizes its address.
The address consists of the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the
eighth bit (which is sent after the address).
When the address is sent, each device in the system compares this address with its own. If there is a match, the device
considers itself addressed and sends an acknowledge signal. Depending on the state of the R/W bit (1=read, 0=write), the
device acts either as a transmitter or a receiver. The combination of the 7-bit address and the R/W bit is used in this docu-
ment to define the slave address as a write address (even) and a read address (odd) pair.
A low-to-high transition during a ACBCLK high period indicates the Stop Condition and ends the transaction of ACBDAT
(see Figure 34).
Addressing Transfer Formats
S
Start Condition
ACBCLK
1
2 3 - 6
7
8
9
Transmitter Stays Off Bus
During Acknowledge Clock
Acknowledge
Signal From Receiver
Data Output
by Transmitter
Data Output
by Receiver
Figure 33. ACCESS.bus Acknowledge Cycle
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PDF描述 |
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| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
| PC87415 | PCI-IDE DMA Master Mode Interface Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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