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參數(shù)資料
| 型號(hào)： | PC87413 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LPC ServerI/O for Servers and Workstations |
| 中文描述： | LPC ServerI /服務(wù)器和工作站 |
| 文件頁(yè)數(shù)： | 113/257頁(yè) |
| 文件大?。?/td> | 3163K |
| 代理商： | PC87413 |
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5.0 X-Bus Extension
(Continued)
Revision 1.2
113
www.national.com
P
5.4.10
These registers control the operation mode of chip select XCSn, where n is from 0 to 3.
Power Well:V
SB
Location:Offset 0Fh (XZM0)
Location:Offset 10h (XZM1)
Location:Offset 11h (XZM2)
Location:Offset 12h (XZM3)
Type:
Varies per bit
X-Bus Select Mode Register (XZM0 to XZM3)
Bit
7
6
5
4
3
2
1
0
Name
LOCKXSCF
WRSTAT
SMIWREN
XCSPOL
XCSTIM
TRANSMD
TRANSPD
Reset
0
0
0
0
0
0
0
0
Bit
Type
Description
7
R/W1S
LOCKXSCF (X-Bus Select Configuration Lock).
Locks the configuration registers of the respective
XCSn signal (both XZCNFn register and XZMn register) by disabling writing to all their bits (including to
itself). An exception to this is the WRSTAT bit of the XZMn register. In addition, it locks the bits in the
XBCNF register. Once set, this bit can be cleared either by the V
DD
Power-Up reset (or Hardware
reset) or by the V
SB
Power-Up reset, according to the VSBLOCK bit in the ACBLKCTL register (see
Section 6.3.4 on page 128). In addition, this bit is cleared by setting the UNLOCKX bit in the
ACBLKCTL register (
PC87417
).
0: Lock Disabled (default)
1: Lock Enabled, protecting the configuration for this chip select
6
R/W1C
WRSTAT (Write Status).
This bit is set if a write to the chip select occurred. Writing 1 to this bit clears
it to 0. WRSTAT is not locked by the LOCKXSCK bit.
0: No write detected (default)
1: Write to the chip select detected
5
R/W or
RO
SMIWREN (SMI-on-Write Enable).
Enables the generation of an SMI, if the WRSTAT bit is set by the
occurrence of a write to the chip select.
0: SMI Disabled (default)
1: SMI Enabled
4
R/W or
RO
XCSPOL (XCS Polarity Control).
Selects the polarity of the XCSn signal.
0: Active low - idle = 1, select = 0 (default)
1: Active high - idle = 0, select = 1
3-2
R/W or
RO
XCSTIM (XCS Timing Control).
Selects the timing of the XCSn signal during read and write
transactions in mode 0. If TRANSMD bit is set to mode 1, the value of these bits is ignored and they
are treated as ‘00’.
Bits
3 2
Function
0 0: Normal XCSn timing for both read and write cycles (default)
0 1: Normal XCSn timing during write cycles; XRD_XEN timing for XCSn during read cycles
1 0: Normal XCSn timing during read cycles; XWR_XRW timing for XCSn during write cycles
1 1: XRD_XEN timing for XCSn during read cycles; XWR_XRW timing for XCSn during write cycles
1
R/W or
RO
TRANSMD (X-Bus Transaction Mode).
Selects the X-Bus transaction mode pertaining to the behavior
of the XWR_XRW and XRD_XEN signals during a transaction.
0: Mode 0 - This is an ISA-like mode. When accessing the XCSn, XWR_XRW functions as an active low
write signal and XRD_XEN functions as an active low read signal (default)
1: Mode 1 - In this mode, when accessing the XCSn, XWR_XRW functions as a read/write signal (high
for a read transaction and low for a write transaction) and XRD_XEN functions as an active high enable
signal
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC87414 | LPC ServerI/O for Servers and Workstations |
| PC87416 | LPC ServerI/O for Servers and Workstations |
| PC87417 | LPC ServerI/O for Servers and Workstations |
| PC87415 | PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | PCI-IDE DMA Master Mode Interface Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC87414 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87415 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PCI-IDE DMA Master Mode Interface Controller |
| PC87415VCG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87416 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
| PC87417 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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