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Chapter 1 Architectural Overview
The Input/Output (I/O) space can be reached by setting the AS (address space)
bit in load and store instructions. Transfers to I/O space, like coprocessor space and
data space transfers, are indicated by the appropriate value appearing on the
DREQT1–0 (data request type) processor pins. I/O space access is only convenient
for assembly level routines. There is typically no convenient way for a high level lan-
guage to indicate an access is to be performed to I/O space rather than data space. For
this reason use of I/O space is often best avoided, unless it is restricted to accessing
some Supervisor maintained peripheral which is best handled via assembly language
code.
The 2–bus 29K family processors support a reduced number of off–chip address
spaces, in fact, only two: Input/Output space, and a combined Instruction/Data
memory space. Accessing both instructions and data via a shared instruction/data bus
simplifies the memory system design. It can also simplify the software; for example,
instruction space and data space can no longer overlap. Consider a 3–bus system
which has physical memory located at address 0x10000 in instruction space and also
different memory located at address 0x10000 in data space. Software errors can oc-
cur regarding accessing the correct memory for address 0x10000. It can also compli-
cate system tasks such as virtual memory management, where separate free–page
lists would have to be kept for the different types of memory.
The Translation Look–Aside buffer (TLB), used to support virtual memory ad-
dressing, supports separate enabling of data and instruction access via the R/W/X
(read/write/execute) enable bits. However, permission checking is only performed
after address translation is performed. It is not possible to have two valid virtual–to–
physical address translations present in the TLB at the same time for the same virtual
address, even if one physical address is for data space and the other instruction space.
This complicates accessing overlapping address spaces via a single 32–bit virtual
space.
Accessing virtual memory has similar characteristics to accessing memory via a
high level language. For example, C normally supports a single address space. It is
difficult and nonportable to have C code which can reach different address spaces.
Except for instruction fetching, all off–chip memory accesses are via load and store
type instructions. The OPT2–0 field for these instructions specifies the size of the
data being transferred: byte, half–word or 32–bit. The compiler assigns OPT field
values for all load and store instructions it generates. Unless via C language exten-
sions or assembly code post–processing, there is no way to set the load and store
instruction address–space–selecting options. Software is simplified by locating all
external peripherals and memory in a single address space; or when a Harvard archi-
tecture is used, by not overlapping the regions of data and instruction memory spaces
used.