302
Evaluating and Programming the 29K RISC Family
The lower 12 address bits will be unmodified by the MMU translation, they will
flow directly to the address pins. The next five address bits (bits 12 to 16) will be used
to select a TLB
set.
See Figure 6-6 for address field composition. If the page size had
been 2K bytes then address bits 11–15 would be used to obtain five bits for TLB set
selection. Whatever the page size, five bits are required to select from one of 32 TLB
sets. The Am29000 processor has actually 64 TLB entries arranged as two per TLB
set.
0
7
15
23
31
Virtual Address Tag Comparison
Address offset within Page
11
TLB set
Figure 6-6.
TLB Field Composition for 4K Byte Page Size
Each TLB entry contains an address translation for a single page. Therefore the
MMU contains translations for a maximum 64 pages. It is possible the address re-
quiring translation does not have a match with any of the current TLB entries, but this
will be discussed later. The virtual address space is divided into 32 sets of equal sized
pages (known as sets 0 to 31). Page 0 starting at address 0 belongs to set 0. Page 1
belongs to set 1 and so on. Pages 32, 64 and many more also belong to set 0. And
likewise page 31, 63 and more belong to set 31. All addresses falling on pages which
are members of the set must obtain an address translation from the TLB entrees
which are associated with the set. This is know as
Set Associative Translation.
If a
page address could be translated by an entry in any TLB, then the translation tech-
nique is known as
Fully Associative.
Compared to full associative mechanisms, set associative translation requires
less chip area to implement than full associative mechanisms, and can more easily
operate at higher speeds. However, there are still many pages which
compete
with
each other to get their address translation stored in a TLB assigned to the associated
TLB set. For this reason the Am29000 processor supports two TLB entries per set.
This is often expressed as “two columns per set”. A page associated with a particular
set can have its address translation located in any of the two possible TLB entries.
This leads to the title: Two–way Set Associative Translation.
To determine which TLB entry has a valid entry for the page currently being
translated, the upper address bits, 17–31 in our 4K byte page example, are compared
with the the VTAG filed in the TLB entry. The VTAG contains the corresponding
upper bits for the TLB entries current translation. If a mach occurs, and other TLB
permission bit field requirements are also satisfied, then the TLB RPN field supplies
the upper address bits for the now translated physical address. In our 4K page exam-
ple the RPN (Real Page Number) field would supply upper address bits 12 to 31,