
429
Chapter 8 Selecting a Processor
Building an Am29200 system with 1/1 SRAM at 20 MHz requires 5 ns memory
access times. These are much more expensive than the 11.25 ns memories required at
16 MHz. To reduce cost, an interleaved SRAM system could be constructed. This
would result in 2/1 SRAM access. However, this achieves only 90% of the
performance on an 1/1 SRAM system operating at 16 MHz. It would be better to
build the slower, less expensive, yet higher performing 16 MHz system.
With 20 MHz memory systems, the Am2920x microcontrollers are operating at
their maximum frequency. As more performance is required, the likelihood of
selecting an Am29240 processor increases. This is particularly true if DRAM–only is
to be used. An Am29240 using 32–bit DRAM–only (2/1) is 151% faster than an
Am29200 using a 3/2 DRAM–only system.
It is possible to build SRAM based systems using an Am29240 processor.
Shown in Table 8-3 are the required memory access times for Am2924x ROM space
memory. The table is based on preliminary AMD data which may change in the
future. The 1/1 access times are given under the 0–Wait column. At 20 MHz a 9 ns
access time must be supported. This is difficult to achieve, and probably not
worthwhile economically. In practice, it would be better to slow the clock speed
down to 19.2 MHz and use 10 ns SRAM devices.
However, the Am29240 system using 32–bit 2/1 DRAM–only has 76% of the
performance of a 32–bit 1/1 SRAM system. The performance benefit of SRAM,
relative to DRAM, is diminished when used with an Am2924x microcontroller. This
is partly due to the 2–cycle requirement for all data writes performed to ROM space.
The 1/1 access is only achieved with instruction fetching and data reading. All data
writes are performed with, at best, 2/2 access times. Conversely, DRAM supports 2/1
for all types of access.
25 MHz Memory Systems
The performance of 25 MHz memory systems is shown in Figure 8-3. These
systems can only be built using Am29240 and Am29243 microcontrollers. At this
speed it is not possible to use 1–cycle first access memory. And, 2/1 SRAM has
poorer performance than 2/1 DRAM due to the 2–cycle data–write limitation.
Scalable Clocking is not available at 20 MHz and above. Hence, all memory
systems must run at the speed of the processor. The fast (2/1) DRAM controller
incorporated into the Am2924x microcontrollers makes DRAM the correct memory
choice with these processors. Additionally, the 2/2 ROM which could be used with
such systems would degrade performance from a DRAM–only system. Hence, it
makes sense to use only a slow 8–bit ROM to initialize the DRAM. Program code,
and initialized data, should be transferred from narrow ROM to DRAM during
program initialization. If a program is too large to fit within a single 8–bit ROM, it
would then make sense to use 16–bit ROM for additional capacity.