
60
Evaluating and Programming the 29K RISC Family
data move operation. Should the operation be interrupted for any reason, the CR field
reports the number of transfers yet to be completed. Channel operation is typically
restarted (if enabled) when an IRET type instruction is issued.
Instruction Environment Registers
Special registers
sr160
and
sr162
, known as FPE and FPS, are the floating–
point environment and status registers. The environment register is used by User
mode programs to establish the required floating–point operations, such as double–
or single–precision, IEEE specification conformance, and exception trap enabling.
The status register reports the outcome of floating–point operations. It is typically
examined as a result of a floating–point operation exception occurring. Only proces-
sors (Am29050) which support floating–point operations directly (free of trapware)
have real
sr161
and
sr162
registers. All other processors appear to have these regis-
ters via trapware support which
creates
virtual registers
.
The integer environment is established by setting special register
sr161
, known
as INTE. There are two control bits which separately enable integer and multiplica-
tion overflow exceptions. If exception detection is enabled, the processor will take
an Out–of–Range trap when an overflow occurs. Only processors (Am29040,
Am29240 and Am29243) which support integer multiply directly (free of trapware)
have a real
sr161
register. All other processors appear to have an
sr161
register via
trapware support.
Additional User Mode Special Registers
Am29050
The Am29050 has an additional special register, shown in Figure 1-21. Register
sr164
, known as EXOP, reports the instruction operation code causing a trap. It is
used by floating–point instruction exceptions. Unlike other 29K processors the
Am29050 directly executes all floating–point instructions. Exception traps can oc-
cur during these operations. When instruction emulation techniques are being used, it
is an easy matter to determine the instruction being emulated at the time of the trap.
However, with direct execution things are not as simple. The processor could ex-
amine the memory at the address indicated by the PC–buffer registers to determine
the relevant instruction opcode. But the Am29050 supports a Harvard memory archi-
tecture and there is no path within the processor to access the instruction memory as if
it were data. The EXOP register solves this problem. Whenever an exception trap is
taken, the EXOP register reports the opcode of the instruction causing the exception.
Users of other 3–bus Harvard type processors such as the Am29000 and
Am29005 should take note; virtualizing the unprotected special registers
sr160–162
requires that the instruction space be readable by the processor (virtualizing, in this
case, means making registers
sr160–162
appear to be accessible even when they are
not physically present). This can only be achieved by connecting the instruction and