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Evaluating and Programming the 29K RISC Family
5.12 ON–CHIP CACHE SUPPORT
First level caches are small on–chip memories which can respond on behalf of
off–chip memory when a processor attempts a memory access. When the required
access is satisfied by the cache, known as a cache
hit
, a performance advantage is
obtained when compared to accessing slower off–chip memory. Caches enable high
performance systems to be constructed without the expense and complexity of fast
system memory.
The 29K family supports a mixture of different cache schemes, see Table 5-1.
Some of the inexpensive devices such as the Am29005 processor and the Am29200
microcontroller have no on–chip cache. Other family members generally have some
kind of instruction memory cache; and in some of the top performing processors, data
cache is provided. The individual processor User’s Manual describes the operation of
the available cache in detail. Chapter 1 outlined the basic cache capabilities of the
family (see sections 1.3–1.9). This section deals with the support code needed to
maintain cache operation. Some cache operations are described in more detail for the
purpose of showing how cache maintenance affects system performance.
When a cache is provided, the 29K family supports two–way set associative
caching. The two–way cache associativity (see section 6.2) provides two possible
locations (blocks or cache entries) for caching any selected memory location. A
block contains four contiguous words from memory and associated tag and status
bit–fields. When a cache miss occurs, and both associated blocks are valid but not
locked (can be displaced), a block is chosen at random for replacement (known as
reload
). Investigations have shown that random replacement can be more successful
than a Least Recently Used (LRU) replacement scheme.
When a 29K processor is reset, the processor disables all caches by setting the
cache disable bit–fields in the CFG configuration register. Cache entries must first be
invalidated before the cache is enabled. Supervisor mode code can perform most
operating system cache maintenance services by simply manipulating the bit–fields
of the CFG register. In addition Supervisor mode privileged instructions are provided
for cache invalidation.
5.13 INSTRUCTION CACHE MAINTENANCE
Instruction cache memory has typically a larger impact on performance than
data cache with the 29k family. This is due to the reduced number of data accesses
required by application code. The reduction is relative to other processors, generally
CISC, which have a small number of on–chip registers. Application data is normally
held in the 128–word register file which is a
cache
of the top of the application
register stack.
The potentially higher performance of a RISC chip is only achieved if the
instruction pipeline is kept effectively busy. The RISC engine is instruction
hungry