Chapter 3 Assembly Language Programming
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the shadow register technique, there must be a delay of one cycle before the register
file can be accessed after
gr1
has been modified.
3.3.4 Accessing Special Register Space
The special registers control the operation of the processor. They are divided
into two groups: those that can be accessed only in Supervisor mode and those which
have unrestricted access. Access of special registers
sr128
and above do not generate
a protection violation when accessed in User mode. Special register space was de-
scribed in section 1.10.2. Not all 29K family members have fully implemented spe-
cial register spaces. In the Supervisor–only accessible space there are a number of
differences due to differences in on–chip resources such as cache memory and hard-
ware breakpoint registers. Because these are not accessible to application code they
do not effect application code portability.
However, some members of the 29K family do not implement, in hardware, all
of the special registers accessible by User mode programs. In particular the floating
point support registers (
sr160–sr162
) are only implemented on processors which di-
rectly support floating–point instructions in hardware. All other family members
virtualize these registers. An attempted access to unimplemented special registers
causes a Protection Violation trap to occur. The trapware code implements the access
and returns the result. Unfortunately, the trapware code does not use the indirect
pointer as they are not set by a protection violation trap. This means the trapware
must read the instruction space to determine the special register being accessed. This
leads to the consequence that the special floating point support registers can not be
virtualized with Harvard memory architectures which do not provide a memory
bridge to enable instruction memory to be accessed as data. The emulation technique
also requires the support of three operating system registers. The trapware is typical-
ly configured to use global registers
ks13–ks15
(
gr93–gr95
) for this task.
Special registers are located in their own register space. They can only be ac-
cessed by the move–from (MFSR) and move–to (MTSR) instructions which transfer
data between special register space and general purpose registers. In addition there is
a MTSRIM instruction which can be used to set a special register with 16–bit im-
mediate data. The indirect pointers can not be used to access special register space.
This imposes some restriction in accessing special registers but in practice is accept-
able. However, where the address of a special register to be accessed is contained in a
general purpose register, the technique shown below can be used. In the example,
lr2
contains the address of the special register to be read with a MFSR instruction. The
example assumes instruction memory can be written to; the required instruction is
built in
gr97
and stored in memory at an address given by
gr98.
The instruction is
then
visited
with a JMPI instruction. A jump instructions target address is
visited
when the jump instruction contains a further jump in its delay slot. The second jump
is in the decode stage of the processor pipeline when the first jump is in execute. This