
296
Evaluating and Programming the 29K RISC Family
The secondary memory is typically a disk. When the MMU identifies the pro-
gram’s need to access data stored on a page currently
out
on disk, it must instruct the
operating system to
page–in
the required page into the physical memory. The page
may be located almost anywhere in physical memory, but the address translation ca-
pability of the MMU will make the page appear at the desired virtual address ac-
cessed by the program. In the process of paging–in from disk, the operating system
may have to
page–out
to disk a page currently located in physical memory. In this
way memory space is made available for the in–coming page.
Within the 29K family, the MMU unit is located on–chip, and is constructed us-
ing
Translation Look–Aside Buffers
(TLBs). This chapter describes in detail how the
TLB hardware operates, and how it can be used to implement a virtual address capa-
bility. The TLBs provide other functions in addition to address translation, such as
separate access permissions for data read, write and instruction execution. These im-
portant functions will be explained and highlighted in example code.
6.1
SRAM VERSUS DRAM PERFORMANCE
As already stated, secondary memory is typically disk. However, it is difficult to
show example code relying on disk controller operation. The example code would be
too large and too much time would be spent dealing with disk controller operation.
This is not our intention. I have chosen to use SRAM devices for
physical
memory
and DRAM and EPROM devices have been chosen to play the role of
secondary
memory.
SRAM devices are much faster than most DRAM memory system arrange-
ments. Thus, by paging the program into SRAM, a very desirable speed gain should
be obtained. Certainly the secondary memory capacity is limited to the typically 1M
to 4M bytes made available by the DRAM and EPROM combination. But programs
will execute from SRAM alone, which may be limited to as little as 128K bytes. For
large programs this is likely to result in SRAM pages being paged out to secondary
DRAM to make space available for incoming pages.
The SRAM will effectively be a memory cache for the secondary DRAM; the
Am29000 processor MMU being used to implement a software controlled cache
mechanism. The performance difference shown by programs executing from SRAM
versus DRAM is large. Figure 6-1 shows the average cycles required per instruction
execution for four well know UNIX utility programs. The influence of memory per-
formance on these benchmarks is likely to be similar to that experienced by large em-
bedded application programs. The DRAM memory system used is termed
4–1
. This
terminology is used throughout this chapter. In this case it means the memory system
requires four cycles for a random access and one cycle for a
burst–mode access.
Burst–mode enables multiple instructions and data to be accessed consecutively
after a single start address has been supplied. The first data or instruction word in the
burst suffers the access penalties of a random access, but subsequent accesses are