
184
Evaluating and Programming the 29K RISC Family
means the second jump must be taken, and only the first instruction of the new
instruction stream is started before execution continues at label
continue
.
const
consth
const
consth
sll
or
store
jmpi
jmp
gr98,I_memory
gr98,I_memory
gr97,0xC6600000 ;MFSR, DEST=gr96, SRCA=0
gr97,0xC6600000
lr2,lr2,8
;lr2 has special register number
lr2,lr2,gr97
;instruction now constructed
0,0,lr2,gr98
;store target instruction
gr98
;visit the target instruction
continue
;must execute the delay slot
;establish instruction address
continue:
The constructed MFSR instruction places the result in register
gr96
. The
lr2
source address value had to be shifted left 8–bits into the SRCA field position of the
MFSR instruction.
3.3.5 Floating–point Accumulators
The Am29050 processor is currently the only member of the 29K family which
directly supports in hardware floating–point arithmetic operations. In addition to
supporting floating–point operations without using trapware emulation, functions
involving multiply–and–accumulate operations are supported by four additional
hardware instructions not implemented in other 29K family members. Sum–of–
product type operations are frequently required by many floating–point intensive ap-
plications, such as matrix multiplication. Implementing this operation efficiently in
hardware makes the Am29050 processor suitable for use in graphics and signal pro-
cessing applications.
The FMAC and DMAC instructions can be used to multiply two general pur-
pose register values together and sum the product with one of the four floating–point
accumulators. The DMAC instruction operates on double–precision operand data
and the FMAC operates on single–precision. Double–precision operands can be ac-
cessed from the register file in a single cycle as the register file is implemented as
64–bits wide, and there is 64–bit wide ports supplying data to the floating–point
execution unit components. Double–precision operands must be aligned on double–
register address boundaries.
The FMSM and DMSM instructions support single and double–precision float-
ing–point multiply–and–sum. One operand for the multiplication is a general pur-
pose register, the second is accumulator 0; the product is summed with the second
instruction operand and the result placed back in the register file. These two instruc-
tions can be used when the multiplier is a fixed value such as with SAXPY (single–
precision A times X plus Y).
The Floating–Point Unit on the Am29050 processor is constructed from a num-
ber of specialized operation pipelines; one for addition/subtraction, one for multi-