
October 13 1995, Draft 1
414
Addendum to –– Evaluating and Programming the 29K RISC Family
reported executed by a trace line has less to do with the instruction retirement
rate and more to do with the run–length between branch instructions. When
an MCU or PCI access occurs at the same time as RLE reporting, the
processed trace indicates all activity on the same processed trace line.
6.
The trace data processing algorithms built into MonTIP need to know the
endian–ness of the 29K target processor. When connection to the analyzer is
established, a window displaying the analyzer control panel will appear.
MonTIP prints a message in this window indicating the endian–ness of the
target processor. If the endian–ness is unknown, MonTIP will continue
operating; but sub word–sized data accesses will only be partially processed.
To fully process data accesses the “Analyzer 1:Name” field provided under
the logic analyzer “Configuration” window should be set to AM29460B or
AM29460L, respectively for big or little endian operation.
7.
If HP16550A logic analyzer cards are being used with the HP16500B system,
then two cards should be wired together in accordance with the HP
Installation Manual. Two analyzer cards provide a total of 12 trace pods. If
the more expensive HP16555A logic analyzer cards are selected, three cards
are required. Once again they should be wired together in accordance with the
HP Installation Manual. Note that even if cards are purchased together, they
may not be interconnected in accordance with HP’s manual
recommendations.
Table 7-6 shows the assignment of analyzer pods to preprocessor connectors.
The analyzer configuration file POD_460._A will format the analyzer cards
for this configuration. (The ._A file name postfix, is because the master
analyzer card is located in card cage slot A.) The POD_460 configuration file
is available from AMD or Corelis. It is important to obtain a copy of the
configuration file, as it is much too time consuming to reassign the
pod–to–label mapping by hand.
Note that the configuration file required for HP16555A cards, although the
same name, is not the same file required to configure HP16550A cards.
8.
A logic analyzer, controlled by UDB, may be attached to a 29K target system
which is not under UDB control. This is the case where a logic analyzer is
used alone, without the utilization of, say, a NetROM. It is also the case when
previously captured trace data is reexamined. To enable 32–bit address
reconstruction, the algorithms built into MonTIP need to know the
processor’s bank profile register (BPR) settings. MonTIP normally
accomplishes this by accessing the DebugCore each time trace data is
fetched. When no DebugCore is present, MonTIP is provided the BPR values
from the udb.rc initialization file.