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Chapter 1 Architectural Overview
speculation be successful. For this to be accomplished, branch prediction techniques
must be employed; more on this is in section 1.7.4.
1.7.3 Register Renaming
It was briefly described in the previous section dealing with read–write
dependency (antidependency), that register renaming can help deal with the conflicts
which arise from the reuse of the same register to hold data values. Of course these
dependencies only arise from the out–of–order instruction issue which occurs with a
superscalar processor. Also described were write–write (output) dependencies,
which occur with even in–order instruction issue when more than one instruction
wishes to write the same result register. Both these types of dependency can be
grouped under the heading
storage conflicts
. Their interference with concurrent
instruction execution is only temporary. Duplication of the result register for the
duration of the conflict can resolve the dependency and enable superscalar
instruction execution to continue.
The temporary result registers are allocated from a
reorder buffer
which
consists of 10 registers and supporting tag information. Every new result value is
allocated a new copy of the original assignment register. Copies are tagged to enable
them to be used as source operands in future instructions. Register renaming is shown
for the example code sequence below.
;original code ;code after register renaming
mul
gr96,lr2,lr5
add
gr97,gr96,1
add
gr96,lr5,1
mul
add
add
RR1,lr2,lr5 ;gr96 = lr2 * lr5
RR2,RR1,1
RR3,lr5,1
The write–write dependency between the first and third instruction is resolved
by renaming register
gr96
to be register
RR3
in the third instruction. The renaming
gr96
to be
RR3
in the third instruction also resolves the read–write dependency
between the second and third instruction Using register renaming, execution of the
third instruction need not be stalled due to storage (register) dependency. Figure 1-7
shows the dependencies before and after register renaming.
Let’s look in more detail at the operation of the reorder buffer. When an instruc-
tion is decoded and placed in the instruction window (in practice, a reservation sta-
tion), a register in the reorder buffer is assigned to hold the instruction result.
Figure 1-8 shows the format of information held in the reorder buffer. When the
instruction is issued from the reservation station and, at a later time, execution com-
pleted, the result is written to the assigned reorder buffer entry.
If a future instruction refers to the result of a previous instruction, the reorder
buffer is accessed to obtain the necessary value. The reorder buffer is accessed via the
contents of the destination–tag field. This is known as a content–addressable
memory access. A parallel search of the reorder buffer is performed. All memory
locations are simultaneously examined to determine if they have the requested data.