
Chapter 3 Assembly Language Programming
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shared resource. Compare instructions are frequently followed by conditional Jump
or Call instructions which depend on the contents of the compare result register.
The second type of compare instruction incorporates a conditional test in the
same instruction cycle accomplishing the comparison. These type of instructions,
known as Assert instructions, allow instruction execution to continue only if the re-
sult of the comparison is TRUE. Otherwise a trap to operating system code is taken.
The trap number is supplied in the field–C (DEST) operand position of the instruc-
tion. Trap numbers 0 to 63 are reserved for Supervisor mode program use. If an As-
sert instruction, with trap number less than 64 is attempted while the processor is op-
erating in User mode, a protection violation trap will be taken. Note, this is will occur
even if the assertion would have been TRUE. Assert instructions are used in proce-
dure prologue and epilogue routines to perform register stack bounds checking (see
Chapter 2). Their fast operation makes them ideal for reducing the overhead of regis-
ter stack support. They are also used as a means of requesting an operating system
support service (system call). In this case a condition known to be FALSE is asserted,
and the trap number for the system call is supplied in instruction field–C. The
Compare instructions are shown in Tables 3–3 and 3–4.
The CPBYTE performs four comparisons simultaneously. The four bytes in the
SRCA operand are compared with the SRCB operand and if any of them match then
Boolean TRUE is placed in the DEST register. The instruction can be very efficiently
used when scanning character strings. In particular, the C programming language
marks the end of character strings with a 0 value. Using the CPBYTE instruction with
SRCB supplying an immediate value 0, the string length can be quickly determined.
3.1.3 Logical
The Logical instructions perform a set of bit–by–bit Boolean functions on
word–length bit strings. All instructions in this class set the ALU Status Register.
These instructions are shown in Table 3-5.
3.1.4 Shift
The Shift instructions (Table 3-6) perform arithmetic and logical shifts on glob-
al and local register data. The one exception is the EXTRACT instruction which op-
erates on double–word data. When EXTRACT is used, SRCA and SRCB operand
registers are concatenated to form a 64–bit data value. This value is then shifted by
the
funnel shifter
by the amount specified by the Funnel Shift Count register (FC).
The high order 32–bits of the shifted result are placed in the DEST register. The fun-
nel shifter can be used to perform barrel shift and rotate operations in a single cycle.
Note, when the SRCA and SRCB operands are the same register, the 32–bit operand
is effectively rotated. The result may be written back to the same register or placed in
a different global or local register (see Figure 3-1). The funnel shifter is useful for
fixing–up
unaligned memory accesses. The two memory words holding the un-