
20
Evaluating and Programming the 29K RISC Family
There are connections for JTAG and a logic analyzer as well as two UARTs via
an 85C30 serial communications controller. The board requires a 5–volt power sup-
ply and there is a small wire–warp area for placement of additional system compo-
nents.
The later rev–B boards have an additional parallel port and Ethernet connection
(10–base–T). An AMD HiLANCE is used for Ethernet communication. The rev–B
board can also support memory system speeds up to 33 MHz.
1.7
A SUPERSCALAR 29K PROCESSOR
AMD representatives have talked at conferences and to the engineering press
about a superscalar 29K processor. No announcements have yet been made about
when such a processor will be available, but it is generally expected to be in the near
future. At the 1994
Microprocessor Forum
, AMD presented a product overview, but
much of the specific details about the processor architecture were not announced.
However, piecing together available information, it is possible to form ideas about
what a superscalar 29K would look like.
This section does not describe a specific processor, but presents the superscalar
techniques which are likely to be utilized. A lead architect of the 29K family, Mike
Johnson, has a text book dealing with “Superscalar Microprocessor Design” ([John-
son 1991]) which covers the technology in depth. It might be expected that many of
the conclusions drawn in Johnson’s book will appear in silicon in a future 29K pro-
cessor.
AMD has stated that future microprocessors will be pin compatible with the cur-
rent 2–bus family members. This indicates that a superscalar 29K will be pin compat-
ible with the Am29030 and Am29040 processors. It is much more likely that the pro-
cessor will take 2–bus form rather than a microcontroller. User mode instruction
compatibility can also be expected. Given the usual performance increments that ac-
company a new processors introduction, it will likely sustain two–times the perfor-
mance of an Am29040 processor. This may be an underestimate, as higher clock rates
or increased use of Scalable Clocking may allow for even higher performance. The
processor is certain to have considerable on–chip instruction and data cache. AMD’s
product overview indicates that 2x, 3x and 4x Scalable Clocking will be supported
and there will be an 8K byte instruction cache and an 8K byte data cache. Also re-
ported was an internal clock speed up to 100 MHz at 3.3–volts.
A superscalar processor achieves higher performance than a conventional sca-
lar processor by executing more than one instruction per cycle. To achieve this it must
have multiple function units which can operate in parallel. AMD has indicated that
the initial superscalar 29K processor will have six function units. And since about
50% of instructions perform integer operations, there will be two integer operation
units, one integer multiplier and one funnel shifter. If a future the processor supports
floating–point operations directly, we can expect to see a floating–point execution