
46
Evaluating and Programming the 29K RISC Family
level communication. This enables very fast UART communication. The Mini-
MON29K DebugCore and OS–boot operating system are initially installed in
EPROM (or Flash); and the DebugCore communicates via an on–chip UART con-
nected to an RS–232 (9–way) connector.
When the NET29K board is used with an Am29205 processor, the 16–bit pro-
cessor bus enables only half of the memory system to be accessed. The board is
physically small, measuring about 5 1/2 x 5 1/2 inches (14cm x 14cm). Debugging is
further supported by JTAG and Logic Analyzer connections. An inexpensive 9–volt
power supply is required.
1.10
REGISTER AND MEMORY SPACE
Most of the 29K instructions operate on information held in various processor
registers. Load and store type instructions are available for moving data between ex-
ternal memory and processor registers. Members of the 29K family generally sup-
port registers in three independent register regions which make up the 29K register
space. These regions are the General Purpose registers, Translation Look–Aside
(TLB) registers, and Special Purpose registers. Members of the 29K family which do
not support Memory Management Unit operation, do not have TLB registers imple-
mented.
There are currently two
core
processors within the 29K family, the Am29000
and the Am29050. Other processors are generally derived from one of these core pro-
cessors. For example, the Am29030 has an Am29000 at its core, with additional sili-
con area being used to implement instruction cache memory and a 2–bus processor
interface. The differences between the core processors and their derivatives is re-
flected in expansions to the special register space.
However, the special register space does appear uniform through out the 29K
family. Generally only those concerned with generating operating system support
code are concerned with the details of the special register space. AMD has specified a
subset of special registers which are supported on all 29K family processors. This
aids in the development and porting of Supervisor mode code.
The core processors support a 3–bus Harvard Architecture, with instructions
and data being held in separate external memory systems. There is one 32–bit bus
each for the two memory systems and a shared 32–bit address bus. Some RISC chips
have a 4–bus system, where there is an address bus for each of the two memory sys-
tems. This avoids the contention for use of a shared address bus. Unfortunately, it also
results in increased pin–count and, consequently, processor cost. The 29K 3–bus pro-
cessors avoid conflicts for the address bus by supporting burst mode addressing and a
large number of on–chip registers. It has been estimated that the Am29000 processor
losses only 5% performance as a result of the shared address bus.
All instruction fetches are directed to instruction memory; data accesses are di-
rected to data memory or I/O space. These two externally accessible spaces consti-