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Chapter 6 Memory Mangement Unit
miss occurs both LRU fields are update. Support software must decide which LRU
field to use and consequently which TLB to update. If the TLBs are allocated to dif-
ferent address regions, the miss address can be used to select the appropriate field.
TLB Entry Word 1 has an additional entry compared with the Am29000 register
format –– the Global Page (GLB) bit; when set, the mapped page can be accessed by
any processes regardless of its process identifier (PID). This can be very useful when
dealing with regions of shared code or data. Multiple processes can accessed, say, a
shared library, without each process having to have valid translation entries for the
memory pages containing the shared information
The Am29040 2–bus processor also supports two TLBs. The TLB register for-
mat is the same as used with the Am29240 microcontroller. However, there are a
number of additional fields implemented in Entry Word 1. The width of data bus used
for external memory accesses can be reduced to 16–bits if the D16 bit is set. When
set, a 32–bit data object is accessed via two 16–bit accesses. The D16 bit simplifies
access to memory or other device which must be accessed with a 16–bit width for-
mat. The PCE bit enables parity checking for the mapped page. Parity is odd or even
depending in the POE bit in the Configuration Register (CFG).
Table 6-1.
PGM Field of the Am29040 Microprocessor TLB
PGM1 PGM0
0
0
1
1
Effect
0
1
0
1
normal (copy–back)
write–through
reserved
none cachable
With virtual addressing in use, the Am29040 TLB entries enable a data cache
maintenance policy to be selected on a perpage bases (see Table 6-1). The default
copy–back policy generaly achieves the highest performance. When the MMU is not
in use (physical addressing) a copy–back policy is applied for cached data. See sec-
tion 5.14.2 for more details about Am29040 data cache policy. Note, when the D16
bit is set, the access is considerd non cacheable.
The example code presented in this chapter for a software controlled cache is
based on the Am29000–type TLB register format. To make the code work with an
Am2924x or Am29040 processor would require some small changes. The code se-
quences requiring modification would be in the construction of TLB entry Word 0
and Word 1. This does not detract from the value of the example code.
6.2.2 Taking a TLB Trap
The address translation performed by the MMU is determined by the trap han-
dler routines which are used to update the TLB registers. When the current processor
status register bits PD and PI are both clear, enabling the MMU hardware for both