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Evaluating and Programming the 29K RISC Family
also perform DMA transfers; this is referred to as internal DMA. DMA is initiated by
an external or internally generated peripheral DMA request.
The only internal peripherals which can generate DMA requests are the parallel
port, the serial port and the video interface. These three devices are described shortly.
There are two external DMA request pins, one for each of the two on–chip DMA con-
trol units. Internal peripherals have a control register field which specifies which
DMA controller their DMA request relates to.
The DMA controllers must be initialized by software before data transfer from,
or to, DRAM takes place. The associated control registers specify the DRAM start
address and the number of transfers to take place. Once the DMA control registers
have been prepared, a DMA transfer will commence immediately upon request with
out any further CPU intervention. Once the DMA transfer is complete the DMA con-
troller may generate an interrupt. The processor may then refresh the DMA control
unit parameters for the next expected DMA transfer.
One of the DMA control units has the special feature of having a duplicate set of
DMA parameter registers. At the end of a DMA transfer, when the primary set of
DMA parameter registers have been exhausted, the duplicate set is immediately co-
pied into the primary set. This means the DMA unit is instantly refreshed and pre-
pared for a further DMA request. Ordinarily the DMA unit is not ready for further use
until the support software has executed, usually via an end of DMA interrupt request.
Just such an interrupt may be generated but it will now be concerned with preparing
parameters for the duplicate control registers for the one–after–next DMA request.
This DMA queue technique is very useful when DMA transfers are occurring to the
video controller. In such case DMA can not be postponed as video imaging require-
ments mean data must be available if image distortion is to be avoided.
External DMA can only occur between DRAM or ROM space and two of the six
PIA address space banks. DMA only supports an 8–bit address field within a PIA ad-
dress bank.
One further note on DMA, the microcontroller does support an external DMA
controller; enabling random access by the external DMA device to DRAM and
ROM. The external DMA unit must activate the associated control pins and place the
address on the microcontroller address bus. In conjunction with the microcontroller,
the external DMA unit must complete the single 32–bit data access.
1.8.6 16–bit I/O Port
The I/O port supports bit programmable access to 16 input or output pins. These
pins can also be used to generate level–sensitive or edge–sensitive interrupts. When
used as outputs, they can be actively driven or used in open collector mode.
1.8.7 Parallel Port
The parallel port is intended for connecting the microcontroller chip to a host
processor, where the controller acts as an intelligent high performance control unit.