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Evaluating and Programming the 29K RISC Family
The cache can be invalidated in a single cycle using an INV or IRETINV type
instruction. However this invalidates all User and Supervisor mode entries. It might
be possible to improve the execution speeds of Supervisor mode code and interrupt
handlers by keeping them locked in the cache. This may also reduce interrupt latency
times but is no doubt at the cost of reduced User mode code execution. The non BTC
processors, that is, the 2–bus processors and microcontroller, provide a means of
locking the cache.
Locking valid blocks (or entries) into the cache is not provided for on a
per–block basis but in terms of the complete cache or one set of the two columns.
When a column is locked, valid blocks are not replaced; invalid blocks will be
replaced and marked valid and locked. Cache locking can be applied before
preloading the cache with instruction sequences critical to performance. Instruction
cache locking is achieved by setting the IL field of the CFG configuration register.
When the cache is locked, an INV type instruction will not cause block invalidation
unless the cache is also disabled. Column 0 and column 1 of each set can be locked or
only column 0 locked. When only column 0 is locked, replacement of blocks in
column 1 continues on a direct mapping basis. That is, there is only one location in the
cache which can cache any particular memory address. This results in increased
cache reload activity which reduces the effectiveness of cache.
As an illustrative exercise, consider the code necessary to invalidate only User
mode cache entries. For a 4K byte Instruction cache there are 1K instructions cached
in 256 blocks of four instructions. Given the two–way–set approach, there are 128
sets; each set containing one block in each of the two columns. The following code
scans the 128 blocks of column 0, and invalidates the block only if the entry is found
to cache User mode code. Note, the cache must be disabled while being accessed via
the Cache Interface (CIR) and Cache Data (CDR) registers. These registers enable
cache tags and data to be directly read and written.
const
mfsr
or
mtsr
gr64, 0x100
gr65, cfg
gr65, gr65, gr64; disbable cache
cfg, gr65
; set the ID–bit
; read CFG register
; write CFG config.
;
const
const32 gr65, 0x10000000; FSEL=01, tag read
const32 gr67, 0x01000000; R/W OR mask
const
gr68, 0
gr64, 128–2
; scan 128 blocks
; zero value
next:
mtsr
mfsr
sll
jmpt
or
mtsr
mtsr
cir, gr65
gr66, cdr
gr66, gr66, 31
gr66, keep
gr66, gr65, gr67; set the RW–bit to write
cir, gr66
; prepare to write tag
cdr, gr68
; write zero into status
; prepare to read tag
; read tag–status word
; test US–bit
; jump if Super. mode
keep: