
October 13 1995, Draft 1
408
Addendum to –– Evaluating and Programming the 29K RISC Family
present disassembled instructions on the analyzer display. Using the Corelis
software, trace label DATA can be displayed in Invasm (inverse assembler)
format without resulting in any conflicts with MonTIP’s access to DATA.
There is no advantage to using the disassemby software, as the analyzer
display shows instructions which are fetched but not necessarily executed.
6.
There are a number of limitations imposed by the Am29040 Traceable Cache
architecture. These where previously discussed in section 7.8 under the
heading
Processing Trace Information
. Very briefly, the complete instruction
flow is reported: Labels, DATA, ADDR, R/_W and I/_D have their values
manipulated to report the instruction which was executed during the traced
cycle.
7.
The trace data processing algorithms built into MonTIP need to know the
endian–ness of the 29K target processor. When connection to the analyzer is
established, a window displaying the analyzer control panel will appear.
MonTIP prints a message in this window indicating the endian–ness of the
target processor. If the endian–ness is unknown, MonTIP will continue
operating; but sub word–sized data accesses will only be partially processed.
To fully process data accesses, the “Analyzer 1:Name” field provided under
the logic analyzer “Configuration” window should be set to AM29040B or
AM29040L, respectively for big or little endian operation.
8.
The MonTIP algorithms are currently restricted to operating with systems
which fetch instructions from 32–bit memory. This does not necessitate that
32–bit ROM emulation be used with NetROM. If application programs are
loaded and execute from 32–bit memory, they can be successfully traced.
However, if interrupt handlers or other support code is run from 8–bit
memory, tracing will not be possible.
9.
can’t reduce capture rules
7.9.5 Corelis PI–Am29460 Preprocessor
A logic analyzer preprocessor simplifies the connection of the analyzer to the
target system. The principles behind its operation were discussed in section 7.8. This
section briefly deals with the operating details encountered with the Am29460
preprocessor. For those simply interesting in getting their preprocessor working, and
not at this stage needing to understand the background behind its operation, proceed
to the section with the subheading
PI–Am29460 Setup and Limitation.
The Traceable Cache information provided by the Am29040 slave processor is
synchronous with program execution. If this approach were taken with the Am29460
microcontroller, the superscalar execution capability would necessitate very high
speed trace reporting. To reduce the slave processor’s information bandwidth