
23
Chapter 1 Architectural Overview
Write–Write Dependency
A second type of data dependency can complicate out–of–order instruction
completion. Examine the code sequence shown below:
mul
add
add
gr96,lr2,lr5
gr97,gr96,1
gr96,lr5,1
;write gr96, gr96 = lr2 * lr5
;write gr96, write–write dependency
The result of the third instruction has an
output dependency
on the first
instruction. The third instruction can not complete before the first. Both instructions
write their results to register
gr96
, and completing the first instruction last would
result in an out–of–date value being held in
gr96
. Steps must be taken to deal with the
data dependency. Because the completion of multiple instructions is dependent on
writing
gr96
with the correct value, this kind of dependence is also known as a
write–write
dependance
.
Scoreboarding or reduced–scoreboarding can also resolve write–write
dependences. Before an instruction is issued, the scoreboard bit for the result register
is tested. If there is a currently in–execute instruction planning on writing to the same
result register, the scoreboard bit will be set. This information can be used to stall
issuing until the result register is available.
The parallel execution possible with out–of–order completion, enables higher
performance than in–order completion, but extra logic is required to deal with data
dependency checking. With in–order instruction issue, instructions can no longer be
issued when a dependency is detected. If instruction issue is to continue when data
dependencies are present, the processor architecture becomes yet more complicated;
but the performance reward is extended beyond that of out–of–order completion
with in–order issue.
Read–Write Dependency
Instruction issuing can continue even when the write–read and write–write
dependencies described above are present. The preceding discussion on data
dependency was restricted to in–order instruction issue. Certainly, when a data
dependency is detected, the unfortunate instruction can not be issued; but this need
not mean that future instructions can not be issued. Of course the future instruction
must be free of any dependencies. With out–of–order instruction issue, instructions
are decoded and placed in an
instruction window
. Instructions can be issued from the
window when they are free of dependencies and there is an available function unit.
The processes of decoding and executing an instruction is separated by the
instruction window, see Figure 1-5. This does not add an additional pipeline stage to
the superscalar processor. The decoder
places
instructions into the window. When an
instruction is free of dependencies it can be issued from the window to a function unit
for execution. The register window could be implemented as a large buffer within the
instruction decode unit, but this leads to a complex architecture. When an instruction