52
Evaluating and Programming the 29K RISC Family
bit is zero. Or, when the more typical table of vectors method is being used by, setting
bit–1 of the handler address. Since handler routines all start on 4–byte instruction
boundaries, bits 0 and 1 of the vector address are not required to hold address in-
formation. The 2–bus and microcontroller members of the 29K family do not support
ROM space and RV bit in the CFG registers is reserved.
Processor Status
Two special registers,
sr1
and
sr2
, are provided for processor status reporting
and control. The two registers OPS (old processor status) and CPS (current processor
status) have the same bit–field format. Each bit position has been assigned a unique
task. Some bit positions are not effective with particular family members. For exam-
ple, the Am29030 processor does not use bit position 15 (CA). This bit is used to indi-
cate coprocessor activity. Only the 3–bus family members support coprocessor op-
eration in this way.
The CPS register reports and controls current processor operation. Supervisor
mode code is often involved with manipulating this register as it controls the enabling
and disabling of interrupts and address translation. When a program execution ex-
ception is taken, or an external event such as an interrupt occurs, the CPS register
value is copied to the OPS register and the processor modifies the CPS register to
enter Supervisor mode before execution continues in the selected exception handling
routine. When returning from the handler routine, the interrupted program is re-
started with an IRET type instruction. Execution of an IRET instruction causes the
OPS register to be copied back to the CPS register, helping to restore the interrupted
program context. Supervisor mode code often prepares OPS register contents before
executing an IRET and starting User mode code execution.
Configuration
Special register
sr3
, known as the configuration control register (CFG), esta-
blishes the selected processor operation. Such options as big or little endian byte or-
der, cache enabling, coprocessor enabling, and more are selected by the CFG setting.
Normally this register value is established at processor boot–up time and is infre-
quently modified.
The original Am29000 (rev C and later) only used the first six bits of the CFG
register for processor configuration. Later members of the family offer the selection
of additional processor options, such as instruction memory cache and early address
generation. Additional options are supported by extensions to the CFG bit–field as-
signment. Because there is no overlap with CFG bit–field assignment across the 29K
family, and family members offer a matrix of functionality, there are often reserved
bit–fields in the CFG register for any particular 29K processor. The function pro-
vided at each bit position is unique and if the function is not provided for by a proces-
sor, the bit position is reserved.