October 13 1995, Draft 1
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Chapter 7 Software Debugging
visor mode code normally arranges for the vector table entry for the trace trap to
cause the debug monitor to gain control of the processor.
The debug monitor, normally MiniMON29K, uses the IRET instruction to re-
start program execution after the Trace trap handler has completed. Execution of an
IRET causes the Old Processor Status register (OPS) to be copied into the CPS regis-
ter before the next program instruction is executed. The TP bit in the OPS is normally
cleared by the debug monitor before the IRET is executed. If the TE bit in the OPS is
set then tracing of the restarted instruction sequence shall continue after executing
the IRET.
Note, when the disable all (DA) bit in the CPS register is set the trace trap cannot
be taken unless the processor supports Monitor mode (described below). Should the
program being debugged issue an instruction such as ASNEQ, it will then take a trap
and the DA bit will become set. The OPS and CPS registers will have the TP bit set
but a trace trap will not be taken. This means that Freeze mode code (trap handlers
which execute with the DA bit set) cannot be debugged by a software debug monitor
unless the processor supports Monitor mode. Most members of the 29K processor
family do not support Monitor mode.
7.2.4 Program Counter register PC2
The instruction following a branch instruction, known as the delay instruction,
is executed regardless of the outcome of the branch. This performance improving
technique requires that two registers be used to record the addresses of the instruc-
tions currently in the execute and decode stages of the processor pipeline. When a
branch is taken the PC0 register contains the address of the target instruction as it en-
ters the decode stage of the pipeline. Register PC1 always contains the address of the
instruction in execute. When the target instruction of a branch enters decode the
instruction in execute is the delay slot instruction following the branch.
Program counter registers PC0 and PC1 are required to restart the processor
pipe–line in the event of a trap or an interrupt occurring. Many of the synchronous
traps, such as a register access privilege violation, cause execution to be stopped with
the address of instruction causing the violation held in PC1 (execute address).
Asynchronous traps, such as an external interrupt, and instruction traps, such as AS-
SERT instructions, cause the address of the instruction following the one in execute
at the time of the interrupt to be held in the PC1 register. In fact when a trap or inter-
rupt is taken the PC register values are frozen and used to restart program execution
later. The frozen PC values are held in a 3 register PC–buffer. Of course, the actual PC
registers continue to be used. Instructions such as MTSR and MFSR (move–to and
move–from special register) can be used to modify the PC–buffer register values.
The address of the instruction previously in execute and now in write–back is
held in the PC2 register. This is very convenient because a debugger can determine
the instruction which was in execute at the time the interrupt or trap occurred. The