33
Chapter 1 Architectural Overview
It is certain that a superscalar 29K processor will incorporate a branch
prediction technique. Given that instruction compatibility is to be maintained, it is
likely that a hardware prediction rather than a software prediction method will be
employed. This will require the processor to keep track of previous branch activity.
An algorithm will likely help with selecting the most frequent branch paths; such as
branches to lower addresses are more often taken then not –– jump at bottom of loop.
1.8
THE Am29200 MICROCONTROLLER
The Am29200
was the first of the 29K family microcontrollers (see
Table 1-3) [AMD 1992b]. To date the Am29205
is the only other microcontroller
added to the family. Being microcontrollers, many of the device pins are assigned I/O
and other dedicated support tasks which reduce system glue logic requirements. For
this reason none of the devices are pin compatible. The system support facilities, in-
cluded within the Am29200 package, make it ideal for many highly integrated and
low cost systems.
The processor supports a 32–bit address space which is divided into a number of
dedicated regions (see Figure 1-12). This means that ROM, for example, can only be
located in the region preallocated for ROM access. When an address value is gener-
ated, the associated control–logic for the region is activated and used to control data
or instruction access for the region.
There is a 32–bit data bus and a separate 24–bit address bus. The rest of the 104
pins used by the device are mainly for I/O and external peripheral control tasks
associated with each of the separate address regions.
By incorporating memory interface logic within the chip, the processor enables
lower system costs and simplified designs. In fact, DRAM devices can be wired di-
rectly to the microcontroller without the need for any additional circuitry.
At the core of the microcontroller is an Am29000 processor. The additional I/O
devices and region control mechanisms supported by the chip are operated by pro-
grammable
registers
located in the
control register region
of memory space. These
control registers are accessible from alternate address locations –– for historical rea-
sons. It is best, and essential if C code is used, to access these registers from the op-
tional word–aligned addresses.
Accessing memory or peripherals located in each address region is achieved
with a dedicated region controller. While initializing the control registers for each
region it is possible to specify the access times and, say, the DRAM refresh require-
ments for memory devices located in the associated region.
Other peripheral devices incorporated in the microcontroller, such as the UART,
are accessed by specific control registers. The inclusion of popular peripheral de-
vices and the associated
glue
logic for peripheral and memory interfaces within a
single RISC chip, enables higher performance at lower costs than existing systems