
October 13 1995, Draft 1
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Addendum to –– Evaluating and Programming the 29K RISC Family
7.2.2 Memory Access Protection
A number of the 29K processor family members are equipped with a Transla-
tion Look–aside buffer (TLB). It is intended for construction of a Memory Manage-
ment Unit (MMU) scheme. A complete description of the TLB operation is given in
Memory Management Unit
(Chapter 6)
.
An MMU is normally used to provide virtual memory support. However, it can
also play an important debugging role, even in embedded applications. Note, this
function is not intended to be performed by the Region Mapping facility provided on
some family members. The Region Mapping facility does not support the address
space granularity supported by the TLB hardware. In addition, Region Mapping in
some cases only allows address mapping to a limited region of physical memory. For
example, on the Am29200 microcontroller, only the DRAM memory and not the
ROM memory can be accessed in virtual address space.
When code is being developed, often an erroneous data reference will occur. If
no memory is located at the particular address then the target memory system should
generate a hardware access error (such as DERR or IERR on some family members).
However, address aliasing often results in the access being performed on some other
address location for which address decoding determines physical memory has been
assigned. This kind of programming bug can be difficult to detect. Using the TLB,
address access errors can be immediately detected and reported to the operating sys-
tems via access protection violations.
The OS–boot operating system, used by many customers, can provide memory
access protection by mapping virtual address to physical addresses in a one–to–one
format. This is adequate for many embedded applications where memory paging
does not occur and application programs can be completely located in available
memory. When an access violation occurs OS–boot informs the MiniMON29K
monitor who reports the violation to the process controlling debugging. The details
of this mechanism are described in later sections.
Whether you intend using OS–boot or some other operating system, it is likely
you would benefit from using the on–chip TLB hardware to support a more powerful
debug environment, via the detection of invalid memory references.
7.2.3 Trace Facility
Using the Trace Facility, a program can be executed one instruction at a time.
This allows the execution of a program to be followed and the state of the processor
to be examined and modified after each instruction has executed.
The 29K family has a four stage pipeline: Fetch, Decode, Execute and Write–
back. Tracing is enabled by setting the Trace enable (TE) bit in the CPS register.
When an instruction passes from the execute stage of the pipeline into the write–back
stage, the TE bit is copied into the TP bit. The Trap Pending (TP) bit is also located in
the CPS register, and when it becomes set the processor takes a trace trap. The Super-